LS-X2280-BASE-PC-N Lattice, LS-X2280-BASE-PC-N Datasheet - Page 6

• Manufacturer Part Number: LS-X2280-BASE-PC-N
• Description: MCU, MPU & DSP Development Tools ispLEVER Base MachXO -2280 Std Dev Kit
• Manufacturer: Lattice

Specifications of LS-X2280-BASE-PC-N

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
The default configuration for jumper JP6 is to configure the TDI from JP7 to be routed to the MachXO first. The
TDO from the MachXO is routed to the ispClock device. TDO from the ispClock is connected to the JTAG header
JP7. However Figure 3 shows the board can be configured to only have the MachXO accessible by the JTAG
header. It can also be configured to only have the ispClock accessible by the JTAG header.
Jumper JP8 controls the TMS routing to the MachXO and the ispClock. The default configuration connects TMS to
both the MachXO and the ispClock. When the MachXO is the only device in the JTAG chain, the ispClock TMS is
pulled high, causing it to always go into Test-Logic-Reset mode. The MachXO has its TMS pin pulled high when the
ispClock is the only device in the JTAG chain.
Figure 3. Programming Interface
Push Buttons and Status LEDs
There are three push-buttons and three LEDs in the south portion of the MachXO Standard Evaluation Board.
Switch S2, the westernmost, asserts the Global Set/Reset input on the MachXO. When the button is pressed, LED
D9 (red), illuminates. This gives clear visual evidence the GSR input has toggled. In order for the GSR to operate, it
is necessary to instantiate the GSR macro in the VHDL/Verilog HDL source.
Immediately adjacent to the MachXO reset switch is the ispClock reset switch (S3). Pressing this button asserts
RESET to the ispClock chip.
Finally, there is a general use push-button (S4). S4 is routed to T11 on the MachXO device. It is normally pulled
high, and when pressed is asserted to ground. When pressed, LED D10 (yellow) illuminates.
Adjacent, westward, to S2 is diode D11 (green). This is a LED tied to a general purpose I/O on the MachXO. This
LED signals that the MachXO is done being programmed. However, it can be used to signal any status desired.
Evaluation bitstreams will tie output pin T6 to drive low, turning D11 on.
Global Output Enable
The MachXO device features a global output enable control. The GOE is routed to JP18, and the factory default
setting on JP18 is to enable the MachXO outputs. The jumper on JP18 can be moved from the default setting to
disable (tri-state) all of the MachXO I/Os.
Table 5. Global Output Enable
MachXO and Support Interfaces
The MachXO Standard Evaluation Board includes basic support features for evaluating the performance and func-
tionality of the MachXO device. This includes a prototyping area permitting arbitrary logic functions to be placed on
MachXO
MachXO
ispClock
ispClock
Only
Only
Jumper Block JP18
and
Jumpers
1-2
2-3
TDI
Jumpers
TMS
Outputs disabled (tri-state)
Outputs enabled
6
Output Enable State
Route
TDI
JTAG
MachXO Standard Evaluation Board
Pin 1
Revisions 001 & 002 User’s Guide
Route
TMS