LS-X2280-BASE-PC-N Lattice, LS-X2280-BASE-PC-N Datasheet - Page 7

• Manufacturer Part Number: LS-X2280-BASE-PC-N
• Description: MCU, MPU & DSP Development Tools ispLEVER Base MachXO -2280 Std Dev Kit
• Manufacturer: Lattice

Specifications of LS-X2280-BASE-PC-N

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
board. There are also locations to insert connectors and resistors. These connections are useful for performing I/O
characterization.
The silk screen markings on the evaluation board are designed to make it easy to locate resources on the board
and related connections to the MachXO.
• Parts are numbered in a consistent fashion. Each part starts at reference designator ‘1’ in the northwest corner
• The alphanumeric pin position of the MachXO 256-ball fpBGA is indicated adjacent to most of the switch inputs,
• A solid white rectangle area near the SMA connectors denotes the positive side of a matched pair. The negative
Prototype Grids
The board includes five 100-mil center-center prototype grid areas consisting of plated through holes with various
connections.
It is important to note the board conventions used to identify the through hole types:
• Any through hole with a square-shaped plated area is not connected to any device on the board, and provided
• Any round through-hole outlined with a thin white silkscreen rectangle is connected to ground.
• All other round through-holes are connected to the MachXO pin as indicated by the silkscreen.
Note: Some prototype grid test points may be connected to “no-connect” (NC) pin locations on the MachXO device.
Consult the MachXO device datasheet for further details regarding the MachXO pinout.
Prototype Grid 1 and 2: Grid 1 is located in the northwest portion of the board. Grid 2 is due south of the MachXO
device. Both areas have an alphanumeric grid located in the silkscreen indicating which plated through hole is
attached to which MachXO pin.
Both grids are intermixed with through holes attached to the ground plane. These ground holes are marked with a
white silkscreened rectangle.
Both grids are also intermixed with unconnected locations. These are indicated with a square-shaped plated area.
For example, starting in the upper-left of Grid 1; location A2 and A3 are unconnected, location A4 is connected to
the MachXO I/O pin A4, etc.
Both grids also have a series of pull-up/pull-down/inline resistors connected to the through holes. Figure 4 shows
how these resistors may be arrayed around the prototype area.
of the board (i.e. R1, C1, U1, L1…). The component number increases by one in a columnar fashion (i.e. south-
ward). When the south edge of the board is reached, the count resumes slightly east, and at the north side of the
board. Thus the highest numbered components will always be in the southeast corner of the board. This same
numbering sequence is applied to the reverse side of the evaluation board.
LED outputs, SMA connectors, and test points on the board. For example, the designator (F3) is located next to
the SMA connector JP2. Thus MachXO pin F3 is connected to the center post of JP2.
side of the matched pair has a white outline rectangle area.
for your convenience.
7
(M12)
MachXO Standard Evaluation Board
Revisions 001 & 002 User’s Guide