ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet
ADUC7034BCPZ-RL
Specifications of ADUC7034BCPZ-RL
Related parts for ADUC7034BCPZ-RL
ADUC7034BCPZ-RL Summary of contents
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FEATURES High precision ADCs Dual channel, simultaneous sampling, 16-bit Σ-Δ ADCs Programmable ADC throughput from kHz On-chip 5 ppm/°C voltage reference Current channel Fully differential, buffered input Programmable gain from 1 to 512 ADC input range: ...
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ADuC7034 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Electrical Specifications ............................................................... 4 Timing Specifications ................................................................ 10 Absolute Maximum Ratings .......................................................... 15 ESD Caution ................................................................................ 15 Pin ...
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MOSI Pin ................................................................................... 110 SCLK Pin ................................................................................... 110 SS Pin ......................................................................................... 110 SPI Register Definitions .......................................................... 110 Serial Test Interface ...................................................................... 114 Serial Test Interface Registers ................................................. 114 Serial Test Interface Output Structure ................................... 116 Using the Serial Test Interface ...
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ADuC7034 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 3 VREF = 1.2 V internal reference, f precision oscillator, all specifications T A Table 1. Parameter Test Conditions/Comments ADC SPECIFICATIONS 1 Conversion Rate Chop off, ADC normal operating mode ...
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Parameter Test Conditions/Comments 13 Voltage Channel 1 No Missing Codes Valid at all ADC update rates 1 Integral Nonlinearity 3, 5 Offset Error Chop off, 1 LSB = 439.5 μV Offset Error 1, 3 Chop on Offset Error Drift Chop ...
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ADuC7034 Parameter Test Conditions/Comments VOLTAGE REFERENCE ADC Precision Reference Internal VREF 1 Power-Up Time Initial Accuracy 1 Measured Temperature Coefficient 22 Reference Long-Term Stability 23 External Reference Input Range 1 VREF Divide-by-2 Initial Error ADC Low ...
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Parameter Test Conditions/Comments 1 LOGIC INPUTS All logic inputs Input Low Voltage (V ) INL Input High Voltage (V ) INH 1 CRYSTAL OSCILLATOR Logic Inputs, XTAL1 Only Input Low Voltage (V ) INL Input High Voltage (V ) INH ...
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ADuC7034 Parameter Test Conditions/Comments R Slave termination resistance SLAVE 28 V Voltage drop at the internal diode SERIAL DIODE Symmetry of Transmit VDD (minimum Propagation Delay 1 Receive Propagation Delay VDD (minimum Symmetry ...
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Parameter Test Conditions/Comments POWER REQUIREMENTS Power Supply Voltages VDD (Battery Supply) 33 REG_DVDD, REG_AVDD Power Consumption 34 I (MCU Normal Mode) MCU clock rate = 10.24 MHz, ADC off DD MCU clock rate = 20.48 MHz, ADC off 1 I ...
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ADuC7034 TIMING SPECIFICATIONS SPI Timing Specifications Table 2. SPI Master Mode Timing—Phase Mode = 1 Parameter Description 1 t SCLK low pulse width SCLK high pulse width SH t Data output valid after SCLK edge DAV t ...
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Table 3. SPI Master Mode Timing—PHASE Mode = 0 Parameter Description 1 t SCLK low pulse width SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data output setup before SCLK edge ...
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ADuC7034 Table 4. SPI Slave Mode Timing—PHASE Mode = 1 Parameter Description SCLK edge SCLK low pulse width SCLK high pulse width SH t Data output valid after SCLK edge DAV ...
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Table 5. SPI Slave Mode Timing—PHASE Mode = 0 Parameter Description SCLK edge SCLK low pulse width SL t SCLK high pulse width Data output valid after SCLK edge DAV t ...
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ADuC7034 LIN Timing Specifications RECESSIVE TRANSMIT INPUT TO TRANSMITTING NODE DOMINANT TH REC (MAX) TH DOM (MAX) V SUP (TRANSCEIVER SUPPLY OF TRANSMITTING NODE) TH REC (MIN) TH DOM (MIN) RxD (OUTPUT OF RECEIVING NODE 1) RxD (OUTPUT OF RECEIVING ...
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ABSOLUTE MAXIMUM RATINGS T = −40°C to +115°C, unless otherwise noted. A Table 6. Parameter Rating AGND to DGND to VSS to IO_VSS −0 +0.3 V VBAT to AGND − +40 V VDD to VSS −0.3 ...
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ADuC7034 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GPIO_5/IRQ1/RxD GPIO_6/TxD GPIO_7/IRQ4 GPIO_8/IRQ5 NOTES CONNECT. 2. THE EXPOSED PAD SHOULD BE CONNECTED TO DGND. Table 7. Pin Function Descriptions Pin No. Mnemonic Type 1 RESET I 2 GPIO_5/IRQ1/RxD I/O ...
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Pin No. Mnemonic Type 11 NTRST I 12 TMS I 13 VBAT I 14 VREF I 15 GND_SW I 18 VTEMP I 19 IIN IIN− I 21, 22 AGND S 24 REG_AVDD S 27 GPIO_0/IRQ0/SS I/O 28 GPIO_1/SCLK ...
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ADuC7034 TYPICAL PERFORMANCE CHARACTERISTICS 0 –0.2 VDD = 4V –0.4 –0.6 –0.8 –1.0 –1.2 –40 – TEMPERATURE (°C) Figure 8. ADC Current Channel Offset vs. Temperature, 10 MHz MCU 0 –40°C –0.5 +25°C –1.0 +115°C –1.5 –2.0 –2.5 ...
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TERMINOLOGY Conversion Rate The conversion rate specifies the rate at which an output result is available from the ADC after the ADC has settled. The Σ-Δ conversion techniques used on this part mean that while the ADC front-end signal is ...
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ADuC7034 THEORY OF OPERATION The ADuC7034 is a complete system solution for battery monitoring automotive applications. This device integrates all of the required features to precisely and intelligently monitor, process, and diagnose 12 V battery parameters, including ...
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ARM7 Exceptions The ARM7 supports five types of exceptions, with a privileged processing mode associated with each type. The five types of exceptions are as follows: • Normal interrupt (IRQ). This is provided to service general-purpose interrupt handling of internal ...
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ADuC7034 The maximum IRQ latency can be similarly calculated, but must allow for the fact that FIQ has higher priority and may delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced ...
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Remap Operation When a reset occurs on the ADuC7034, execution starts automatically in the factory-programmed internal configuration code. This so-called kernel is hidden and cannot be accessed by user code. If the ADuC7034 is in normal mode, it executes the ...
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ADuC7034 RESET There are four kinds of resets: external reset, power-on reset, watchdog reset, and software reset. The RSTSTA register indicates the source of the last reset and can be written to by user code to initiate a software reset ...
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FLASH/EE MEMORY The ADuC7034 incorporates Flash/EE memory technology on chip to provide the user with nonvolatile, in-circuit reprogrammable memory space. Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased, with the ...
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ADuC7034 FEE0CON Register Name: FEE0CON Address: 0xFFFF0E08 Default Value: 0x07 Access: Read/write access Function: This 8-bit register is written by user code to control the operating modes of the Flash/EE memory controller. Table 13. Command Codes in FEE0CON Code Command ...
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Command Sequence for Executing a Mass Erase Given the significance of the mass erase command, a specific code sequence must be executed to initiate this operation: 1. Set Bit 3 in FEE0MOD. 2. Write 0xFFC3 in FEE0ADR. 3. Write 0x3CFF ...
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ADuC7034 FEE0DAT Register Name: FEE0DAT Address: 0xFFFF0E0C Default Value: 0x0000 Access: Read/write access Function: This 16-bit register contains the data either read from written to the Flash/EE memory. FLASH/EE MEMORY SECURITY The Flash/EE memory ...
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Temporary Protection Temporary protection can be set and removed by writing directly into the FEE0HID MMR. This register is volatile and, therefore, protection is only in place for as long as the part remains powered on. The protection setting is ...
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ADuC7034 CODE EXECUTION TIME FROM SRAM AND FLASH/EE This section describes SRAM and Flash/EE access times during execution for applications where execution time is critical. Execution from SRAM Fetching instructions from SRAM takes one clock cycle because the access time ...
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ADuC7034 KERNEL The ADuC7034 features an on-chip kernel resident in the top the Flash/EE code space. After any reset event, this kernel copies the factory-calibrated data from the manufacturing data space into the various on-chip peripherals. The ...
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ADuC7034 PAGE ERASED? 0x14 = 0xFFFFFFFF YES LIN COMMAND INITIALIZE ON-CHIP PERIPHERALS TO FACTORY- CALIBRATED STATE NO YES JTAG MODE? NTRST = 1 NO YES KEY PRESENT? 0x14 = 0x27011970 NO YES CHECKSUM PRESENT? 0x14 = CHECKSUM NO FLAG PAGE ...
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MEMORY-MAPPED REGISTERS The memory-mapped register (MMR) space is mapped into the top the MCU memory space and accessed by indirect addressing, loading, and storage commands through the ARM7-banked registers. An outline of the memory-mapped register bank for ...
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ADuC7034 COMPLETE MMR LISTING In the following MMR tables, addresses are listed in hexadecimal code. Access types include R for read, W for write, and RW for read and write. Table 18. IRQ Address Base = 0xFFFF0000 Access Address Name ...
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Access Address Name Byte Type 0x0340 T2LD 4 RW 0x0344 T2VAL 4 R 0x0348 T2CON 2 RW 0x034C T2CLRI 1 W 0x0360 T3LD 2 RW 0x0364 T3VAL 2 R 0x0368 T3CON 0x036C T3CLRI 1 W 0x0380 T4LD ...
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ADuC7034 Table 22. ADC Address Base = 0xFFFF0500 Access Address Name Byte Type 0x0500 ADCSTA 2 R 0x0504 ADCMSKI 1 RW 0x0508 ADCMDE 1 RW 0x050C ADC0CON 2 RW 0x0510 ADC1CON 2 RW 0x0518 ADCFLT 2 RW 0x051C ADCCFG 1 ...
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Table 23. UART Base Address = 0XFFFF0700 Access Address Name Byte Type 0x0700 COMTX 1 W COMRX 1 R COMDIV0 1 RW 0x0704 COMIEN0 1 RW COMDIV1 1 RW 0x0708 COMIID0 1 R 0x070C COMCON0 1 RW 0x0710 COMCON1 1 ...
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ADuC7034 Table 26. STI Base Address = 0xFFFF0880 Access Address Name Byte Type 0x0880 STIKEY0 4 W 0x0884 STICON 2 RW 0x0888 STIKEY1 4 W 0x088C STIDAT0 2 RW 0x0890 STIDAT1 2 RW 0x0894 STIDAT2 2 RW Table 27. SPI ...
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Table 29. Flash/EE Base Address = 0xFFFF0E00 Access Address Name Byte Type 0x0E00 FEE0STA 1 R 0x0E04 FEE0MOD 1 RW 0x0E08 FEE0CON 1 RW 0x0E0C FEE0DAT 2 RW 0x0E10 FEE0ADR 2 RW 0x0E18 FEE0SIG 3 R 0x0E1C FEE0PRO 4 RW ...
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ADuC7034 16-BIT SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTERS The ADuC7034 incorporates two independent sigma-delta (Σ-Δ) analog-to-digital converters (ADCs), namely, the current channel ADC (I-ADC) and the voltage/temperature channel ADC (V-/T-ADC). These precision measurement channels integrate on-chip buffering, a programmable gain amplifier, 16-bit Σ-Δ ...
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Figure 17. Current ADC, Top-Level Overview Rev Page 41 of 136 ADuC7034 07116-015 ...
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ADuC7034 VOLTAGE/TEMPERATURE CHANNEL ADC (V-/T-ADC) The voltage/temperature channel ADC (V-/T-ADC) converts additional battery parameters, such as voltage and temperature. The input to this channel can be multiplexed from one of three input sources, namely, an external voltage, an external tempera- ...
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ADC GROUND SWITCH The ADuC7034 features an integrated ground switch pin, GND_SW (Pin 15). This switch allows the user to dynamically disconnect the ground from external devices and instead use either a direct connection to ground or a connection to ...
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ADuC7034 ADC MMR INTERFACE The ADC is controlled and configured through several MMRs that are described in detail in the ADC Status Register to Low Power Voltage Reference Scaling Factor Registersections. All bits defined in the top eight MSBs (Bits[15:8]) ...
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Bit Description 1 Voltage conversion result ready bit. Set by hardware as soon as a valid voltage conversion result is written in the voltage data register (ADC1DAT MMR) if the voltage channel ADC is enabled also set at ...
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ADuC7034 ADC Mode Register Name: ADCMDE Address: 0xFFFF0508 Default Value: 0x00 Access: Read/write Function: The ADC mode MMR is an 8-bit register that configures the mode of operation of the ADC subsystem. Table 35. ADCMDE MMR Bit Designations Bit Description ...
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Current Channel ADC Control Register Name: ADC0CON Address: 0xFFFF050C Default Value: 0x0000 Access: Read/write Function: The current channel ADC control MMR is a 16-bit register that is used to configure the I-ADC. Note: If the current ADC is reconfigured via ...
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ADuC7034 Voltage/Temperature Channel ADC Control Register Name: ADC1CON Address: 0xFFFF0510 Default Value: 0x0000 Access: Read/write Function: The voltage/temperature channel ADC control MMR is a 16-bit register that is used to configure the V-/T-ADC. Note: If the VBAT attenuator input is ...
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ADC Filter Register Name: ADCFLT Address: 0xFFFF0518 Default Value: 0x0007 Access: Read/write Function: The ADC filter MMR is a 16-bit register that controls the speed and resolution of the on-chip ADCs. Note: If ADCFLT is modified, the current and voltage/temperature ...
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ADuC7034 Table 39. ADC Conversion Rates and Settling Times Chop Enabled Averaging Factor Disabled Disabled Disabled Disabled Disabled Enabled Disabled Enabled Enabled N additional time of approximately 60 μs per ADC is required before the first ADC is ...
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ADC Configuration Register Name: ADCCFG Address: 0xFFFF051C Default Value: 0x00 Access: Read/write Function: The 8-bit ADC configuration MMR controls extended functionality related to the on-chip ADCs. Table 41. ADCCFG MMR Bit Designations Bit Description 7 Analog ground switch enable. Set ...
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ADuC7034 Current Channel ADC Data Register Name: ADC0DAT Address: 0xFFFF0520 Default Value: 0x0000 Access: Read only Function: This ADC data MMR holds the 16-bit conversion result from the I-ADC. The ADC does not update this MMR if the ADC0 conversion ...
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Temperature Channel ADC Offset Calibration Register Name: ADC2OF Address: 0xFFFF0538 Default Value: Part specific, factory programmed Access: Read/write Function: This ADC offset MMR holds a 16-bit offset calibration coefficient for the temperature channel. The register is configured at power-on with ...
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ADuC7034 Current Channel ADC Result Counter Limit Register Name: ADC0RCL Address: 0xFFFF0548 Default Value: 0x0001 Access: Read/write Function: This 16-bit MMR sets the number of conversions required before an ADC interrupt can be generated. By default, this register is set ...
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Low Power Voltage Reference Scaling Factor Register Name: ADCREF Address: 0xFFFF057C Default Part specific, factory programmed Value: Access: Read/write. Care should be taken not to write to this register. Function: This MMR allows user code to correct for the initial ...
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ADuC7034 ADC Low Power Plus Mode In low power plus mode, the I-ADC channel is enabled in a mode almost identical to low power mode (ADCMDE[4:3]). However, in this mode, the I-ADC gain is fixed at 512 and the ADC ...
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FREQUENCY (kHz) Figure 22. Modified Sinc3 Digital Filter Response at f (ADCFLT = 0x0087) In ADC normal power mode, the maximum ADC ...
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ADuC7034 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 20 FREQUENCY (kHz) Figure 26. Typical Digital Filter Response at f ADC In ADC low power mode, the Σ-Δ modulator clock of the ADC is no longer ...
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ADC CALIBRATION As shown in detail in the top-level diagrams (Figure 17 and Figure 18), the signal flow through all ADC channels can be described in as follows input voltage is applied through an input buffer (and through ...
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ADuC7034 Understanding the Offset and Gain Calibration Registers The output of a typical block in the ADC signal flow (described in the ADC Sinc3 Digital Filter Response section through the Using the Offset and Gain Calibration section) can be consid- ...
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POWER SUPPLY SUPPORT CIRCUITS The ADuC7034 incorporates two on-chip low dropout (LDO) regulators that are driven directly from the battery voltage to generate a 2.6 V internal supply. This 2.6 V supply is then used as the supply voltage for ...
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ADuC7034 ADUC7034 SYSTEM CLOCKS The ADuC7034 integrates a very flexible clocking system that allows clock generation from one of three sources: an integrated on-chip precision oscillator, an integrated on-chip low power oscillator external watch crystal. These three options ...
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The operating mode, clocking mode, and programmable clock divider are controlled using two MMRs, PLLCON and POWCON, and the status of the PLL is indicated by PLLSTA. PLLCON controls the operating mode of the clocking system, and POWCON controls both ...
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ADuC7034 PLLCON Prewrite Key Register Name: PLLKEY0 Address: 0xFFFF0410 Access: Write only Key: 0x000000AA Function: PLLKEY0 is the PLLCON prewrite key. PLLCON is a keyed register that requires a 32-bit key value to be written before and after PLLCON. PLLCON ...
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POWCON Register Name: POWCON Address: 0xFFFF0408 Default Value: 0x079 Access: Read/write Function: This 8-bit register allows user code to dynamically enter various low power modes and modify the clock divider that controls the speed of the ARM7TDMI core. Table 45. ...
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ADuC7034 LOW POWER CLOCK CALIBRATION The low power 131 kHz oscillator can be calibrated using either the precision 131 kHz oscillator or an external 32.768 kHz watch crystal. Two dedicated calibration counters and an oscillator trim register are used to ...
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OSC0TRM Register Name: OSC0TRM Address: 0xFFFF042C Default Value: 0xX8 Access: Read/write Function: This 8-bit register controls the low power oscillator trim. Table 46. OSC0TRM MMR Bit Designations Bit Description Reserved. Should be written as 0s ...
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ADuC7034 PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM There are 16 interrupt sources on the ADuC7034 that are controlled by the interrupt controller. Most interrupts are generated from the on-chip peripherals, such as the ADC and UART. The ARM7TDMI CPU core only ...
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Normal Interrupt (IRQ) Request The IRQ request is the exception signal allowed to enter the processor in IRQ mode used to service general-purpose interrupt handling of internal and external events. All 32 bits of the IRQSTA MMR are ...
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ADuC7034 Programmed Interrupts Because the programmed interrupts are not maskable, they are controlled by another register, SWICFG, that writes into both IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG registers at the same time. The 32-bit register dedicated to ...
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TIMERS The ADuC7034 features five general-purpose timer/counters. • Timer0, or the lifetime timer • Timer1, or general-purpose timer • Timer2, or the wake-up timer • Timer3, or the watchdog timer • Timer4, or the STI timer The five timers in ...
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ADuC7034 ARM7TDMI AMBA CORE CLOCK LOW POWER OSCILLATOR GPIO HIGH PRECISION OSCILLATOR XTAL CORE CLOCK (F ) CORE DOMAIN As shown in Figure 32, the MMR logic and core timer logic reside in separate and asynchronous clock domains. Any data ...
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Starting Timer2 When starting Timer2 recommended to first load Timer2 with the required TxLD value. Next, start the timer by setting the T2CON bits as required. This enables the timer, but only once the T2CON bits have been ...
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ADuC7034 TIMER0—LIFETIME TIMER Timer0 is a general-purpose, 48-bit up counter or a 16-bit up/down counter timer with a programmable prescaler. Timer0 can be clocked from either the core clock or the low power 32.768 kHz oscillator with a prescaler of ...
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LOW POWER 32.768kHz OSCILLATOR PRECISION 32.768kHz OSCILLATOR EXTERNAL 32.768kHz WATCH CRYSTAL CORE CLOCK FREQUENCY Timer0 Control Register Name: T0CON Address: 0xFFFF030C Default Value: 0x00000000 Access: Read/write Function: This 32-bit MMR configures the mode of operation for Timer0. Table 52. T0CON ...
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ADuC7034 TIMER1 Timer1 is a general-purpose, 32-bit up/down counter with a programmable prescaler. The prescaler source can be the low power 32.768 kHz oscillator, the core clock, or from one of two external GPIOs. This source can be scaled by ...
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Timer1 Capture Register Name: T1CAP Address: 0xFFFF0330 Default Value: 0x00000000 Access: Read only Function: This 32-bit register holds the 32-bit value captured by an enabled IRQ event. Table 53. T1CON MMR Bit Designations Bit Description 8-bit postscaler. ...
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ADuC7034 TIMER2—WAKE-UP TIMER Timer2 is a 32-bit wake-up up/down counter timer with a programmable prescaler. The prescaler is clocked directly from one of four clock sources, namely, the core clock (which is the default selection), the low power 32.768 kHz ...
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Timer2 Control Register Name: T2CON Address: 0xFFFF0348 Default Value: 0x0000 Access: Read/write Function: This 16-bit MMR configures the mode of operation of Timer2. Table 54. T2CON MMR Bit Designations Bit Description Reserved Clock source ...
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ADuC7034 TIMER3—WATCHDOG TIMER Timer3 has two modes of operation: normal mode and watchdog mode. The watchdog timer is used to recover from an illegal software state. When enabled, it requires periodic servicing to prevent it from forcing a reset of ...
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Timer3 Control Register Name: T3CON Address: 0xFFFF0368 Default Value: 0x0000 Access: Read/write Function: This 16-bit MMR configures the mode of operation of Timer3 as described in Table 55. Table 55. T3CON MMR Bit Designations Bit Description Reserved. ...
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ADuC7034 TIMER4—STI TIMER Timer4 is a general-purpose, 16-bit up/down counter timer with a programmable prescaler. Timer4 can be clocked from the core clock or the low power 32.768 kHz oscillator with a prescaler of 1, 16, 256, or 32,768. Timer4 ...
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Table 56. T4CON MMR Bit Designations Bit Description Reserved. 17 Event select bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event Event ...
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ADuC7034 GENERAL-PURPOSE I/O The ADuC7034 features nine general-purpose bidirectional input/output (GPIO) pins. In general, many of the GPIO pins have multiple functions that can be configured by user code. By default, the GPIO pins are configured in GPIO mode. All ...
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Table 57. External GPIO Pin to Internal Port Signal Assignments Port GPIO PIN PORT SIGNAL Port0 GPIO_0 P0.0 IRQ0 SS GPIO_1 P0.1 SCLK GPIO_2 P0.2 MISO GPIO_3 P0.3 MOSI GPIO_4 P0.4 ECLK 1 P0.5 1 P0.6 Port1 GPIO_5 P1.0 IRQ1 ...
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ADuC7034 GENERAL-PURPOSE I/O REGISTERS GPIO Port0 Control Register Name: GP0CON Address: 0xFFFF0D00 Default Value: 0x11100000 Access: Read/write Function: This 32-bit MMR selects the pin function for each Port0 pin. Table 58. GP0CON MMR Bit Designations Bit Description ...
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GPIO Port1 Control Register Name: GP1CON Address: 0xFFFF0D04 Default Value: 0x10000000 Access: Read/write Function: This 32-bit MMR selects the pin function for each Port1 pin. Table 59. GP1CON MMR Bit Designations Bit Description Reserved. These bits are ...
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ADuC7034 GPIO Port2 Control Register Name: GP2CON Address: 0xFFFF0D08 Default Value: 0x01000000 Access: Read/write Function: This 32-bit MMR selects the pin function for each Port2 pin. Table 60. GP2CON MMR Bit Designations Bit Description Reserved. These bits ...
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GPIO Port0 Data Register Name: GP0DAT Address: 0xFFFF0D20 Default Value: 0x000000XX Access: Read/write Function: This 32-bit MMR configures the direction of the GPIO pins assigned to Port0 (see Table 57). This register also sets the output value for GPIO pins ...
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ADuC7034 GPIO Port1 Data Register Name: GP1DAT Address: 0xFFFF0D30 Default Value: 0x000000XX Access: Read/write Function: This 32-bit MMR configures the direction of the GPIO pins assigned to Port1 (see Table 57). This register also sets the output value for GPIO ...
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GPIO Port2 Data Register Name: GP2DAT Address: 0xFFFF0D40 Default Value: 0x000000XX Access: Read/write Function: This 32-bit MMR configures the direction of the GPIO pins assigned to Port2 (see Table 57). This register also sets the output value for GPIO pins ...
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ADuC7034 GPIO Port0 Set Register Name: GP0SET Address: 0xFFFF0D24 Access: Write only Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to set them high only. User code can accomplish this using the GP0SET MMR without ...
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GPIO Port2 Set Register Name: GP2SET Address: 0xFFFF0D44 Access: Write only Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to set them high only. User code can accomplish this using the GP2SET MMR without having ...
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ADuC7034 GPIO Port1 Clear Register Name: GP1CLR Address: 0xFFFF0D38 Access: Write only Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to clear them low only. User code can accomplish this using the GP1CLR MMR without ...
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HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE The ADuC7034 integrates several high voltage circuit functions that are controlled and monitored through a registered interface consisting of two MMRs, namely, HVCON and HVDAT. The HVCON register acts as a command byte interpreter, allowing ...
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ADuC7034 HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE REGISTERS High Voltage Interface Control Register Name: HVCON Address: 0xFFFF0804 Default Value: Updated by kernel Access: Read/write Function: This 8-bit register acts as a command byte interpreter for the high voltage control interface. Bytes ...
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High Voltage Data Register Name: HVDAT Address: 0xFFFF080C Default Value: Updated by kernel Access: Read/write Function: HVDAT is a 12-bit register that is used to hold data to be written indirectly to and read indirectly from the following high voltage ...
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ADuC7034 High Voltage Configuration0 Register Name: HVCFG0 Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read/write Function: This 8-bit register controls the function of high voltage circuits on the ADuC7034. This register is not an ...
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High Voltage Configuration1 Register Name: HVCFG1 Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read/write Function: This 8-bit register controls the function of high voltage circuits on the ADuC7034. This register is not an MMR ...
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ADuC7034 High Voltage Monitor Register Name: HVMON Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read only Function: This 8-bit, read only register reflects the status of the enabled high voltage features. This register is ...
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High Voltage Status Register Name: HVSTA Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read only, but should only be read on a high voltage interrupt Function: This 8-bit, read only register reflects a change ...
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ADuC7034 WAKE-UP (WU) PIN The wake-up (WU) pin is a high voltage GPIO controlled through HVCON and HVDAT. Wake-Up (WU) Pin Circuit Description By default, the WU pin is configured as an output with an internal 10 kΩ pull-down resistor ...
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HANDLING INTERRUPTS FROM THE HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE An interrupt controller is integrated in the high voltage circuits. If the interrupt controller is enabled through IRQEN[16], one of six high voltage sources can assert the high voltage interrupt (IRQ3) ...
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ADuC7034 UART SERIAL INTERFACE The ADuC7034 features a 16,450-compatible UART. The UART is a full-duplex, universal, asynchronous receiver/transmitter. A UART performs serial-to-parallel conversion on data characters received from a peripheral device and performs parallel-to-serial conversion on data characters received from ...
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UART REGISTER DEFINITION The UART interface consists of the following nine registers: • COMTX: 8-bit transmit register • COMRX: 8-bit receive register • COMDIV0: divisor latch (low byte) • COMDIV1: divisor latch (high byte) • COMCON0: line control register • ...
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ADuC7034 Table 80. COMCON0 MMR Bit Designations Bit Name 7 DLAB 6 BRK EPS 3 PEN 2 STOP WLS UART Control Register 1 Name: COMCON1 Address: 0xFFFF0710 Default Value: 0x00 Access: Read/write Function: This ...
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UART Status Register 0 Name: COMSTA0 Address: 0xFFFF0714 Default Value: 0x60 Access: Read only Function: This 8-bit read only register reflects the current status of UART. Table 82. COMSTA0 MMR Bit Designations Bit Name 7 N/A 6 TEMT 5 THRE ...
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ADuC7034 UART Interrupt Enable Register 0 Name: COMIEN0 Address: 0xFFFF0704 Default Value: 0x00 Access: Read/write Function: The 8-bit register enables and disables the individual UART interrupt sources. Table 83. COMIEN0 MMR Bit Designations Bit Name N/A 3 ...
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UART Fractional Divider Register Name: COMDIV2 Address: 0xFFFF072C Default Value: 0x0000 Access: Read/write Function: This 16-bit register controls the operation of the fractional divider for the ADuC7034. Table 85. COMDIV2 MMR Bit Designations Bit Name 15 FBEN ...
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ADuC7034 SERIAL PERIPHERAL INTERFACE The ADuC7034 features a complete hardware serial peripheral interface (SPI) on chip. SPI is an industry-standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, that is, full duplex. ...
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SPI Control Register Name: SPICON Address: 0xFFFF0A10 Default Value: 0x0000 Access: Read/write Function: The 16-bit MMR configures the serial peripheral interface. Table 88. SPICON MMR Bit Designations Bit Description Reserved. 12 Continuous transfer enable. Set by the ...
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ADuC7034 SPI Status Register Name: SPISTA Address: 0xFFFF0A00 Default Value: 0x00 Access: Read only Function: The 8-bit MMR represents the current status of the serial peripheral interface. Table 89. SPISTA MMR Bit Designations Bit Description Reserved. 5 ...
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SPI Receive Register Name: SPIRX Address: 0xFFFF0A04 Default Value: 0x00 Access: Read only Function: This 8-bit MMR contains the data received using the serial peripheral interface. SPI Transmit Register Name: SPITX Address: 0xFFFF0A08 Access: Write only Function: Write to this ...
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ADuC7034 SERIAL TEST INTERFACE The ADuC7034 incorporates single-pin serial test interface (STI) ports that can be used for end-customer evaluation or diagnostics of finished production units. The STI port transmits from bytes of data in 12-bit packets. ...
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Serial Test Interface Control Register Name: STICON Address: 0xFFFF0884 Default Value: 0x0000 Access: Read/write access, write protected by two key registers (STIKEY0 and STIKEY1). A write access to STICON is only completed correctly if the following triple write sequence is ...
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ADuC7034 SERIAL TEST INTERFACE OUTPUT STRUCTURE The serial test interface is a high voltage output that incorporates a low-side driver, short-circuit protection, and diagnostic pin readback capability. The output driver circuit configuration is shown in Figure 44. REF1 PIN READBACK ...
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LIN (LOCAL INTERCONNECT NETWORK) INTERFACE The ADuC7034 features high voltage physical interfaces between the ARM7 MCU core and an external LIN bus. The LIN interface operates as a slave only interface, operating from 1 kBaud to 20 kBaud, and it ...
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ADuC7034 LIN Hardware Synchronization Status Register Name: LHSSTA Address: 0xFFFF0780 Default Value: 0x00 Access: Read only Function: The LHS status register is an 8-bit register whose bits reflect the current operating status of the LIN interface. Table 91. LHSSTA MMR ...
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LIN Hardware Synchronization Control Register 0 Name: LHSCON0 Address: 0xFFFF0784 Default Value: 0x0000 Access: Read/write Function: The LHS control register is a 16-bit register that is used in conjunction with the LHSCON1 register to configure the LIN mode of operation. ...
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ADuC7034 Bit Description 6 Mode of operation bit. Set user code to select BSD mode of operation. Cleared user code to select LIN mode of operation. 5 Enable compare interrupt bit. Set to 1 ...
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LIN Hardware Synchronization Timer0 Register Name: LHSVAL0 Address: 0xFFFF0788 Default Value: 0x0000 Access: Read only Function: The 16-bit, read only LHSVAL0 register holds the value of the internal LIN synchronization timer. The LIN synchronization timer is clocked from an internal ...
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ADuC7034 LIN Frame Data Transmission and Reception When the break symbol and synchronization byte have been correctly received, data is transmitted and received via the COMTX and COMRX MMRs after UART is configured to the required baud rate. To configure ...
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Example LIN Hardware Synchronization Routine Consider the following C-source code LIN initialization routine. void LIN_INIT(void ) { char HVstatus; GP2CON = 0x110000; LHSCON0 = 0x1; do{ HVDAT = 0x02; HVCON = 0x08; do{ HVstatus = HVCON; } while(HVstatus & 0x1); ...
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ADuC7034 Using this configuration, LHSVAL1 begins to count on the first falling edge received on the LIN bus. If LHSVAL1 exceeds the value written to LHSVAL1, in this case 0x3F, a break compare interrupt is generated. On the next falling ...
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LIN Diagnostics The ADuC7034 features the capability to nonintrusively monitor the current state of the LIN pin. This readback functionality is implemented using GPIO_11. The current state of the LIN pin is contained in GP2DAT[4 also possible to ...
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ADuC7034 BIT SERIAL DEVICE (BSD) INTERFACE BSD is a pulse-width modulated signal with three possible states: sync, 0, and 1. These are detailed, along with their associated tolerances, in Table 94. The frame length is 19 bits, and communication occurs ...
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BSD RELATED MMRS The ADuC7034 emulates the BSD communication protocol using a software (bit bang) interface with some hardware assis- tance from the LIN hardware synchronization logic. In effect, the ADuC7034 BSD interface uses the following protocols: • An internal ...
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ADuC7034 BSD COMMUNICATION FRAME To transfer data between a master and slave, or vice versa, the construction of a BSD frame is required. A BSD frame contains seven key components: pause/sync, direction (DIR) bit, slave address, register address, data, parity ...
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INITIALIZE BSD HARDWARE/ SOFTWARE RECEIVE SYNCHRONIZATION PULSES RECEIVE DIRECTION BIT RECEIVE SLAVE ADDRESS RECEIVE REGISTER ADDRESS RECEIVE FIRST PARITY BIT RECEIVE DATA TRANSMIT DATA FROM MASTER RECEIVE SECOND TRANSMIT SECOND PARITY BIT TRANSMIT ACK/NACK Figure 56. BSD Slave Node State ...
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ADuC7034 PART IDENTIFICATION Two registers mapped into the MMR space are intended to allow user code to identify and trace manufacturing lot ID information, part ID number, silicon mask revision, and kernel revision. This information is contained in the SYSSER0 ...
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System Serial ID Register 1 Name: SYSSER1 Address: 0xFFFF023C Default Value: 0x00000000 (updated by kernel at power-on) Access: Read/write Function: At power-on, this 32-bit register holds the part ID number, the silicon mask revision number, and the kernel revision number ...
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ADuC7034 System Assembly Lot ID Register Name: SYSALI Address: 0xFFFF0560 Default Value: 0x00000000 (updated by kernel at power-on) Access: Read/write Function: At power-on, this 32-bit register holds the lower half of the assembly lot ID. For example, if the assembly ...
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SCHEMATIC This example schematic represents a basic functional circuit implementation. Additional components need to be added to ensure that the system meets any EMC and other overvoltage/overcurrent compliance requirements. VBATT 10µF IN+ SHUNT BATTERY GROUND TERMINAL REG_AVDD NTC JTAG ADAPTOR ...
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... OUTLINE DIMENSIONS BSC SQ PIN 1 INDICATOR VIEW 1.00 12° MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range ADuC7034BCPZ −40°C to +115°C ADuC7034BCPZ-RL −40°C to +115° RoHS Compliant Part. 7.00 0.60 MAX 0.60 MAX 37 36 TOP 6.75 BSC SQ 0.50 0. 0.30 ...
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NOTES Rev Page 135 of 136 ADuC7034 ...
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ADuC7034 NOTES ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07116-0-5/10(B) Rev Page 136 of 136 ...