ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 132
![IC,Battery Management,LLCC,48PIN,PLASTIC](/photos/6/50/65022/cp-48-8_sml.jpg)
ADUC7034BCPZ-RL
Manufacturer Part Number
ADUC7034BCPZ-RL
Description
IC,Battery Management,LLCC,48PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.ADUC7034BCPZ-RL.pdf
(136 pages)
Specifications of ADUC7034BCPZ-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI, UART/USART
Peripherals
POR, PSM, Temp Sensor, WDT
Number Of I /o
9
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 115°C
Package / Case
48-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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ADuC7034
System Assembly Lot ID Register
Name:
Address:
Default Value:
Access:
Function:
For example, if the assembly lot ID is 01308640, SYSALI contains
0x38363430, and T1LD contains 0x30313330 at power-up.
System Kernel Checksum Register
Name:
Address:
Default Value:
Access:
Function:
Table 99. FEE0ADR System Identification MMR Bit Designations
Bit
15 to 4
3 to 0
SYSALI
0xFFFF0560
0x00000000 (updated by kernel at power-on)
Read/write
At power-on, this 32-bit register holds the
lower half of the assembly lot ID.
SYSCHK
0xFFFF0240
0x00000000 (updated by kernel at power-on)
Read/write
At power-on, this 32-bit register holds the
kernel checksum.
0x0 = ADuC7030
0x2 = ADuC7032
0x3 = ADuC7033
0x4 = ADuC7034
0x6 = ADuC7036
Others = reserved for future use
Description
Reserved
ADuC703x family ID
Rev. B | Page 132 of 136
System Identification Register
Name:
Address:
Default Value:
Access:
Function:
Note:
FEE0ADR
0xFFFF0E10
Nonzero
Read/write
This 16-bit register dictates the address acted
upon by any Flash/EE command executed via
FEE0CON.
This MMR is also used to identify the
ADuC7034 family member and prerelease
silicon revision.
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