ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 8

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7034
Parameter
LIN VERSION1.3 SPECIFICATION
LIN VERSION 2.0 SPECIFICATION
BSD INPUT/OUTPUT
WAKE-UP
SERIAL TEST INTERFACE
PACKAGE THERMAL
Symmetry of Transmit
Symmetry of Receive Propagation
t
SPECIFICATIONS
R
V
Receive Propagation Delay
D1
D2
Baud Rate
Input Leakage Current
Output Low Voltage (V
Output High Voltage (V
Short-Circuit Output Current (I
Input Low Voltage (V
Input High Voltage (V
VDD
Input Leakage Current
V
V
V
V
Monoflop Timeout
Short-Circuit Output Current (I
Baud Rate
Input Leakage Current
VDD
V
V
V
V
Thermal Shutdown
Thermal Impedance (θ
SYM
dV
dV
SLAVE
dt
dt
SERIAL DIODE
OH
OL
IH
IL
OH
OL
IH
IL
Propagation Delay
Delay
1
30
30
1
1
1
1
28
29
1, 31
1
INL
INH
JA
OL
)
OH
)
)
)
32
)
1
o(sc)
o(sc)
)
)
Test Conditions/Comments
Slave termination resistance
Voltage drop at the internal diode
VDD (minimum) = 7 V
VDD (minimum) = 7 V
VDD (minimum) = 7 V
Bus load conditions (C
1 nF||1 kΩ ; 6.8 nF||660 Ω; 10 nF||500 Ω
Slew rate
Dominant and recessive edges, VBAT = 18 V
Slew rate
Dominant and recessive edges, VBAT = 7 V
Symmetry of rising and falling edge, VBAT = 18 V
Symmetry of rising and falling edge, VBAT = 7 V
Bus load conditions (CBUS||RBUS): 1 nF||1 kΩ,
6.8 nF||660 Ω, 10 nF||500 Ω
Duty Cycle 1, TH
0.581 × VBAT, V
D1 = t
Duty Cycle 2, TH
0.422 × VBAT, V
D2 = t
Input high = VDD, or input low = IO_VSS
V
R
Supply voltage range at which the WU pin is
functional
Input high = VDD
Input low = IO_VSS
Output high level
Output low level
Input high level
Input low level
Timeout period
R
Input high = VDD, or input low = IO_VSS
Supply voltage range for which STI is functional
Output high level
Output low level
Input high level
Input low level
48-lead LFCSP, stacked die
LOAD
LOAD
BSD
= VDD = 12 V
= 300 Ω, C
= 500 Ω, C
BUS_REC(MIN)
BUS_REC(MAX)
SUP
/(2 × t
SUP
REC(MAX)
REC(MIN)
/(2 × t
BUS
BUS
= 7.0 V … 18 V, t
= 7.0 V … 18 V; t
= 91 nF, R
= 2.4 nF, R
BIT
= 0.284 × VBAT, TH
= 0.744 × VBAT, TH
BIT
BUS
)
)
Rev. B | Page 8 of 136
||R
BUS
LIMIT
LIMIT
):
= 39 Ω
= 39 Ω
BIT
BIT
= 50 μs,
= 50 μs,
DOM(MIN)
DOM(MAX)
=
=
Min
20
0.4
−4
−2
1
0.5
−5
−4
0.396
1164
−50
0.8 VDD
40
0.7 VDD
7
0.4
−50
5
4.6
0.6
100
−50
7
0.6 VDD
0.6 VDD
140
Typ
30
0.7
2
1200
80
1.3
140
150
45
Max
47
1
+4
6
+2
3
3
+5
+4
0.581
1236
+50
1.2
200
1.8
18
2.1
+50
2
1.2
2
40
+70
18
0.4 VDD
0.4 VDD
160
Unit
kΩ
V
μs
μs
μs
V/ μs
V/ μs
μs
μs
bps
μA
V
V
mA
V
V
V
mA
μA
V
V
V
V
sec
mA
kbps
μA
V
V
V
V
V
°C
°C/W