ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 31
![IC,Battery Management,LLCC,48PIN,PLASTIC](/photos/6/50/65022/cp-48-8_sml.jpg)
ADUC7034BCPZ-RL
Manufacturer Part Number
ADUC7034BCPZ-RL
Description
IC,Battery Management,LLCC,48PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.ADUC7034BCPZ-RL.pdf
(136 pages)
Specifications of ADUC7034BCPZ-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI, UART/USART
Peripherals
POR, PSM, Temp Sensor, WDT
Number Of I /o
9
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 115°C
Package / Case
48-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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ADuC7034 KERNEL
The ADuC7034 features an on-chip kernel resident in the top
2 kB of the Flash/EE code space. After any reset event, this kernel
copies the factory-calibrated data from the manufacturing data
space into the various on-chip peripherals. The peripherals
calibrated by the kernel are as follows:
•
•
•
•
•
•
•
•
User MMRs that can be modified by the kernel and differ from
their POR default values are as follows:
•
•
•
•
•
•
•
•
Power supply monitor (PSM)
Precision oscillator
Low power oscillator
REG_AVDD/REG_DVDD
Low power voltage reference
Normal mode voltage reference
Current ADC (offset and gain)
Voltage/temperature ADC (offset and gain)
R0 to R15
GP0CON/GP2CON
SYSCHK
ADCMDE/ADC0CON
FEE0ADR/FEE0CON/FEE0SIG
HVDAT/HVCON
HVCFG0/HVCFG1
T3LD
Rev. B | Page 31 of 136
The ADuC7034 also features an on-chip LIN downloader.
A flow chart of the execution of the kernel is shown in Figure 15.
The current revision of the kernel can be derived from SYSSER1,
as described in Table 98.
After a POR reset, the watchdog timer is disabled once the kernel
code is exited. For the duration of the kernel execution, the
watchdog timer is active with a timeout period of 500 ms. This
ensures that when an error occurs in the kernel, the ADuC7034
automatically resets. After any other reset, the watchdog timer
maintains user code configuration for the period of the kernel
and is refreshed just prior to kernel exit. A minimum watchdog
period of 30 ms is required to allow correct LIN downloader
operation. If LIN download mode is entered, the watchdog is
periodically refreshed.
Normal kernel execution time, excluding LIN download, is
approximately 5 ms. It is only possible to enter and leave LIN
download mode through a reset.
SRAM is not modified during normal kernel execution; rather,
SRAM is modified during a LIN download kernel execution.
Note that even with NTRST = 0, user code is not executed unless
Address 0x14 contains either 0x27011970 or the checksum of
Page 0 excluding Address 0x14. If Address 0x14 does not contain
this information, user code is not executed and LIN download
mode is entered. During kernel execution, JTAG access is disabled.
With NTRST = 1, user code is always executed.
ADuC7034
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