ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 124

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7034
Using this configuration, LHSVAL1 begins to count on the first
falling edge received on the LIN bus. If LHSVAL1 exceeds the
value written to LHSVAL1, in this case 0x3F, a break compare
interrupt is generated.
On the next falling edge, LHSVAL0 begins counting. LHSVAL0
monitors the number of falling edges and compares this with
the value written to LHSCON1[7:4]. In this example, the number
of edges to monitor is six falling edges of the LIN frame or five
falling edges of the sync byte. When this number of falling
RESETS AND
COUNTING
LHSVAL1
STARTS
while((GP2DAT & 0x10 ) == 0 )
{}
LHSCON0 = 0x4;
IRQEN = 0x800;
LHSVAL1 = 0x3F
INTERRUPT IS
GENERATED
COMPARE
BREAK
LHSVAL0 STARTS
COUNTING
START
BIT
// Wait until LIN bus returns high
// Enable LHS to detect break condition ungate RX line
// Disable all Interrupts except break compare interrupt
// Enable UART interrupt
// The UART is now configured and ready to be used for LIN
t
BIT
COUNTING AND A
STOP INTERRUPT
LHSVAL0 STOPS
IS GENERATED
Figure 51. Example LIN Configuration
Rev. B | Page 124 of 136
UART IS CONFIGURED,
DISABLED EXCEPT
BREAK COMPARE
LHS INTERRUPTS
edges is received, a stop condition interrupt is generated. It is at
this point that the UART is configured to receive the protected
identifier.
The UART must be gated via LHSCON0[8] before the LIN bus
returns high. If the LIN bus returns high when UART is not
gated, UART communication errors may occur. This process is
shown in detail in Figure 51. Example code to ensure this is as
follows:
STOP
BIT
START
BIT
RECEIVING DATA
VIA UART
ID0
BEGINS
ID1
ID2
ID3
ID4
ID5
P0
P1
STOP
BIT