ADUC7061BCPZ32-RL Analog Devices Inc, ADUC7061BCPZ32-RL Datasheet - Page 11

• Manufacturer Part Number: ADUC7061BCPZ32-RL
• Description: DUAL 24-BIT AFE AND ARM 7 I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7061BCPZ32-RL

• Design Resources: USB Based Temperature Monitor Using ADuC7061 and an External RTD (CN0075) 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 2.625 V
• Data Converters: A/D 5x24b, 8x24b, D/A 1x14b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI Timing
Table 3. SPI Master Mode Timing (Phase Mode = 1)
Parameter
t
t
t
t
t
t
t
t
t
1
Table 4. SPI Master Mode Timing (Phase Mode = 0)
Parameter
t
t
t
t
t
t
t
t
t
t
1
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
SL
SH
DAV
DOSU
DSU
DHD
DF
DR
SR
SF
t
t
UCLK
UCLK
= 97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL.
= 97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL.
(POLARITY = 0)
(POLARITY = 1)
Description
SCLOCK low pulse width
SCLOCK high pulse width
Data output valid after SCLOCK edge
Data input setup time before SCLOCK edge
Data input hold time after SCLOCK edge
Data output fall time
Data output rise time
SCLOCK rise time
SCLOCK fall time
Description
SCLOCK low pulse width
SCLOCK high pulse width
Data output valid after SCLOCK edge
Data output setup before SCLOCK edge
Data input setup time before SCLOCK edge
Data input hold time after SCLOCK edge
Data output fall time
Data output rise time
SCLOCK rise time
SCLOCK fall time
SCLOCK
SCLOCK
MOSI
MISO
t
DAV
t
SH
Figure 3. SPI Master Mode Timing (Phase Mode = 1)
t
DSU
MSB IN
t
DHD
1
MSB
1
t
Rev. B | Page 11 of 108
SL
1
1
t
DF
Min
1 × t
2 × t
t
DR
BITS 6 TO 1
UCLK
UCLK
BITS 6 TO 1
Min
1 × t
2 × t
UCLK
UCLK
t
SR
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
30
30
30
30
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
30
30
30
30
t
LSB IN
SF
ADuC7060/ADuC7061
HCLK
HCLK
LSB
HCLK
HCLK
Max
25
90
40
40
40
40
Max
25
40
40
40
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns