ADUC7061BCPZ32-RL Analog Devices Inc, ADUC7061BCPZ32-RL Datasheet - Page 26

• Manufacturer Part Number: ADUC7061BCPZ32-RL
• Description: DUAL 24-BIT AFE AND ARM 7 I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7061BCPZ32-RL

• Design Resources: USB Based Temperature Monitor Using ADuC7061 and an External RTD (CN0075) 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 2.625 V
• Data Converters: A/D 5x24b, 8x24b, D/A 1x14b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7060/ADuC7061
MEMORY MAPPED REGISTERS
The memory mapped register (MMR) space is mapped into the
upper two pages of the memory array and is accessed by
indirect addressing through the ARM7 banked registers.
The MMR space provides an interface between the CPU and all
on-chip peripherals. All registers, except the core registers, reside
in the MMR area. All shaded locations shown in Figure 12 are
unoccupied or reserved locations and should not be accessed by
user software. Figure 12 shows the full MMR memory map.
The access time for reading from or writing to an MMR
depends on the advanced microcontroller bus architecture
(AMBA) bus used to access the peripheral. The processor has
two AMBA buses: the advanced high performance bus (AHB)
used for system modules and the advanced peripheral bus
(APB) used for a lower performance peripheral. Access to the
AHB is one cycle, and access to the APB is two cycles. All
peripherals on the ADuC706x are on the APB except for the
Flash/EE memory, the GPIOs, and the PWM.
Rev. B | Page 26 of 108
0xFFFFFFFF
0xFFFF0FC0
0xFFFF0D50
0xFFFF0D00
0xFFFF0A14
0xFFFF0A00
0xFFFF048C
0xFFFF0F80
0xFFFF0E24
0xFFFF0E00
0xFFFF0948
0xFFFF0900
0xFFFF0730
0xFFFF0700
0xFFFF0620
0xFFFF0600
0xFFFF0570
0xFFFF0500
0xFFFF0490
0xFFFF0470
0xFFFF0450
0xFFFF0420
0xFFFF0404
0xFFFF0394
0xFFFF0380
0xFFFF0370
0xFFFF0360
0xFFFF0350
0xFFFF0340
0xFFFF0334
0xFFFF0320
0xFFFF0238
0xFFFF0220
0xFFFF0140
0xFFFF0000
Figure 12. Memory Mapped Registers
PLL AND OSCILLATOR
GENERAL-PURPOSE
GENERAL-PURPOSE
SYSTEM CONTROL
FLASH CONTROL
CONTROLLER
REFERENCE
WATCHDOG
REMAP AND
INTERFACE
SELECTION
INTERRUPT
BAND GAP
CONTROL
WAKE-UP
SPI/I
TIMER
TIMER
TIMER
TIMER
UART
PWM
GPIO
DAC
ADC
SPI
I
2
C
2
C