AM29LV256MH113REI AMD (ADVANCED MICRO DEVICES), AM29LV256MH113REI Datasheet - Page 12

• Manufacturer Part Number: AM29LV256MH113REI
• Description: Flash Memory IC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29LV256MH113REI

• Memory Size: 256Mbit
• Package/case: 56-TSOP
• Access Time, Tacc: 110nS
• Mounting Type: Surface Mount
• Supply Voltage: 3V

For example, a V
the 1.8 or 3 volt levels, driving and receiving signals to
and from other 1.8 or 3 V devices on the same data
bus.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See
to the AC
fications and to
to the DC Characteristics table for the active current
specification on reading array data.
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. The page size of
the device is 4 words/8 bytes. The appropriate page is
selected by the higher address bits A(max)–A2. Ad-
dress bits A1–A0 in word mode (A1–A-1 in byte mode)
determine the specific word within a page. This is an
asynchronous operation; the microprocessor supplies
the specific word location.
The random or initial page access is equal to t
t
the locations specified by the microprocessor falls
within that page) is equivalent to t
deasserted and reasserted for a subsequent access,
the access time is t
cesses are obtained by keeping the “read-page ad-
dresses” constant and changing the “intra-read page”
addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
10
CE
and subsequent page read accesses (as long as
“Reading Array Data”
IL
Read-Only Operations
, and OE# to V
Figure 13
I/O
IH
of 1.65–3.6 volts allows for I/O at
.
ACC
IH
or t
for the timing diagram. Refer
.
for more information. Refer
CE
. Fast page mode ac-
table for timing speci-
IL
PACC
. CE# is the power
. When CE# is
D A T A S H E E T
ACC
Am29LV256M
or
Unlock Bypass mode, only two write cycles are re-
quired to program a word, instead of four. The
“Word/Byte Program Command Sequence”
has details on programming data to the device using
both standard and Unlock Bypass command se-
quences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device.
space that each sector occupies.
Refer to the DC Characteristics table for the active
current specification for the write mode. The
acteristics
and timing diagrams for write operations.
Write Buffer
Write Buffer Programming allows the system write to a
maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming
time than the standard programming algorithms. See
“Write Buffer”
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster manufacturing throughput
at the factory.
If the system asserts V
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sector
groups, and uses the higher voltage on the pin to re-
duce the time required for program operations. The
system would use a two-cycle program command se-
quence as required by the Unlock Bypass mode. Re-
moving V
to normal operation. Note that the WP#/ACC pin must
not be at V
programming, or device damage may result. WP# has
an internal pullup; when unconnected, WP# is at V
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the
lect Command Sequence
tion.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
HH
section contains timing specification tables
HH
from the WP#/ACC pin returns the device
for more information.
for operations other than accelerated
HH
Autoselect Mode
Table 2
on this pin, the device auto-
sections for more informa-
indicates the address
December 16, 2005
and
AC Char-
Autose-
section
IH
.