AM29LV256MH113REI AMD (ADVANCED MICRO DEVICES), AM29LV256MH113REI Datasheet - Page 13

• Manufacturer Part Number: AM29LV256MH113REI
• Description: Flash Memory IC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29LV256MH113REI

• Memory Size: 256Mbit
• Package/case: 56-TSOP
• Access Time, Tacc: 110nS
• Mounting Type: Surface Mount
• Supply Voltage: 3V

and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
(Note that this is a more restricted voltage range than
V
V
the standby current will be greater. The device re-
quires standard access time (t
when the device is in either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
Refer to the
current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Refer to the
sleep mode current specification.
December 16, 2005
IH
IO
.) If CE# and RESET# are held at V
± 0.3 V, the device will be in the standby mode, but
DC Characteristics
DC Characteristics
table for the automatic
table for the standby
CE
) for read access
IH
, but not within
IO
D A T A S H E E T
± 0.3 V.
ACC
Am29LV256M
+
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
at V
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Refer to the
rameters and to
Output Disable Mode
When the OE# input is at V
disabled. The output pins are placed in the high
impedance state.
IL
but not within V
AC Characteristics
Figure 15
SS
±0.3 V, the standby current will
for the timing diagram.
IH
, output from the device is
CC4
tables for RESET# pa-
SS
). If RESET# is held
±0.3 V, the device
RP
, the
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