AM29LV256MH113REI AMD (ADVANCED MICRO DEVICES), AM29LV256MH113REI Datasheet - Page 4

• Manufacturer Part Number: AM29LV256MH113REI
• Description: Flash Memory IC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29LV256MH113REI

• Memory Size: 256Mbit
• Package/case: 56-TSOP
• Access Time, Tacc: 110nS
• Mounting Type: Surface Mount
• Supply Voltage: 3V

GENERAL DESCRIPTION
The Am29LV256M is a 256 Mbit, 3.0 volt single power
supply flash memory devices organized as 16,777,216
words or 33,554,432 bytes. The device has a 16-bit
wide data bus that can also function as an 8-bit wide
data bus by using the BYTE# input. The device can be
programmed either in the host system or in standard
EPROM programmers.
An access time of 100, 110, or 120 ns is available.
Note that each access time has a specific operating
voltage range (V
specified in the
ing Information
56-pin TSOP or Fortified BGA package. Each device
has separate chip enable (CE#), write enable (WE#)
and output enable (OE#) controls.
Each device requires only a single 3.0 volt power
supply for both read and write functions. In addition to
a V
(WP#/ACC) input provides shorter programming times
through increased current. This feature is intended to
facilitate factory throughput during system production,
but may also be used in the field if desired.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or
monitor the Ready/Busy# (RY/BY#) output to deter-
mine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces com-
mand sequence overhead by requiring only two write
cycles to program data instead of four.
The VersatileI/O™ (V
tem to set the voltage levels that the device generates
RELATED DOCUMENTS
For a comprehensive information on MirrorBit prod-
ucts, including migration information, data sheets, ap-
plication notes, and software drivers, please see
www.amd.com
tion
mentation.
closely related to this product:
2
→
CC
MirrorBit
input, a high-voltage accelerated program
The following is a partial list of documents
→
→
Product Selector Guide
CC
sections. The device is offered in a
Flash Information
Flash Memory
) and an I/O voltage range (V
IO
) control allows the host sys-
→
→
Product Informa-
Technical Docu-
and the
D A T A S H E E T
Order-
IO
), as
Am29LV256M
and tolerates on the CE# control input and DQ I/Os to
the same voltage level that is asserted on the V
Refer to the Ordering Information section for valid V
options.
Hardware data protection measures include a low
V
tions during power transitions. The hardware sector
group protection feature disables both program and
erase operations in any combination of sector groups
of memory. This can be achieved in-system or via pro-
gramming equipment.
The Erase Suspend/Erase Resume feature allows
the host system to pause an erase operation in a given
sector to read or program any other sector and then
complete the erase operation. The Program Sus-
pend/Program Resume feature enables the host sys-
tem to pause a program operation in a given sector to
read any other sector and then complete the program
operation.
The hardware RESET# pin terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.
The device reduces power consumption in the
standby mode when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.
The SecSi
128-word/256-byte area for code or data that can be
permanently protected. Once this sector is protected,
no further changes within the sector can occur.
The Write Protect (WP#/ACC) feature protects the
first or last sector by asserting a logic low on the WP#
pin.
AMD MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec-
tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.
MirrorBit™ Flash Memory Write Buffer Programming
and Page Buffer Read
Implementing a Common Layout for AMD MirrorBit
and Intel StrataFlash Memory Devices
Migrating from Single-byte to Three-byte Device IDs
CC
detector that automatically inhibits write opera-
TM
(Secured Silicon) Sector provides a
December 16, 2005
IO
pin.
IO