CY8C3665AXI-010 Cypress Semiconductor Corp, CY8C3665AXI-010 Datasheet - Page 10

• Manufacturer Part Number: CY8C3665AXI-010
• Description: PSOC3
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C36xxr

Specifications of CY8C3665AXI-010

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 67MHz
• Number Of I /o: 62
• Eeprom Size: 1K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 32KB (32K x 8)
• Data Converters: A/D 2x12b, D/A 4x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: TQFP
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Rad Hardened: No
• Processor Series: CY8C36
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 67 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 0.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 62
• Eeprom Memory Size: 1KB
• Ram Memory Size: 4KB
• Cpu Speed: 67MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3. Pin Descriptions
IDAC0, IDAC1, IDAC2, IDAC3. Low resistance output pin for
high current DACs (IDAC).
OpAmp0out, OpAmp1out
High current output of uncommitted opamp.
Extref0, Extref1. External reference input to the analog system.
OpAmp0–, OpAmp1–
input to uncommitted opamp.
OpAmp0+, OpAmp1+
Noninverting input to uncommitted opamp.
GPIO. General purpose I/O pin provides interfaces to the CPU,
digital peripherals, analog peripherals, interrupts, LCD segment
drive, and CapSense.
I2C0: SCL, I2C1: SCL. I
on an address match. Any I/O pin can be used for I
wake from sleep is not required.
I2C0: SDA, I2C1: SDA. I
on an address match. Any I/O pin can be used for I
wake from sleep is not required.
Ind. Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi. 32.768 kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi. 4 to 33 MHz crystal oscillator pin.
nTRST. Optional JTAG Test Reset programming and debug port
connection to reset the JTAG connection.
Document Number: 001-53413 Rev. *J
Notes
14. GPIOs with opamp outputs are not recommended for use with CapSense.
15. This feature on select devices only. See
Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance
[14]
[15]
[15]
2
2
C SCL line providing wake from sleep
, OpAmp2–, OpAmp3–
, OpAmp2+, OpAmp3+
C SDA line providing wake from sleep
[15]
, OpAmp2out, OpAmp3out
Plane
Vssd
Ordering Information
[14]
PRELIMINARY
Vddd
[15]
[15]
2
2
C SCL if
C SDA if
on page 99 for details.
. Inverting
.
[15]
.
Vssd
SIO. Special I/O provides interfaces to the CPU, digital
peripherals and interrupts with a programmable high threshold
voltage, analog comparator, high sink current, and high
impedance state when the device is unpowered.
SWDCK. Serial wire debug clock programming and debug port
connection.
SWDIO. Serial wire debug input and output programming and
debug port connection.
SWV. Single wire viewer debug output.
TCK. JTAG test clock programming and debug port connection.
TDI. JTAG test data in programming and debug port connection.
TDO. JTAG test data out programming and debug port
connection.
TMS. JTAG test mode select programming and debug port
connection.
USBIO, D+. Provides D+ connection directly to a USB 2.0 bus.
May be used as a digital I/O pin. Pins are Do Not Use (DNU) on
devices without USB.
USBIO, D–. Provides D– connection directly to a USB 2.0 bus.
May be used as a digital I/O pin. Pins are Do Not Use (DNU) on
devices without USB.
Vboost. Power sense connection to boost pump.
Vbat. Battery supply to boost pump.
Vcca. Output of analog core regulator and input to analog core.
Requires a 1-µF capacitor to Vssa. Regulator output not for
external use.
PSoC
Vssa
Vdda
®
3: CY8C36 Family Datasheet
Plane
Vssa
Page 10 of 111
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