CY8C3665AXI-010 Cypress Semiconductor Corp, CY8C3665AXI-010 Datasheet - Page 95

• Manufacturer Part Number: CY8C3665AXI-010
• Description: PSOC3
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C36xxr

Specifications of CY8C3665AXI-010

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 67MHz
• Number Of I /o: 62
• Eeprom Size: 1K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 32KB (32K x 8)
• Data Converters: A/D 2x12b, D/A 4x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: TQFP
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Rad Hardened: No
• Processor Series: CY8C36
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 67 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 0.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 62
• Eeprom Memory Size: 1KB
• Ram Memory Size: 4KB
• Cpu Speed: 67MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.8.3 Interrupt Controller
Table 11-69. Interrupt Controller AC Specifications
11.8.4 JTAG Interface
Table 11-70. JTAG Interface AC Specifications
11.8.5 SWD Interface
Table 11-71. SWD Interface AC Specifications
11.8.6 SWV Interface
Table 11-72. SWV Interface AC Specifications
Document Number: 001-53413 Rev. *J
f_TCK
T_TDI_setup
T_TMS_setup
T_TDI_hold
T_TDO_valid
T_TDO_hold
f_SWDCK
T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK
T_SWDI_hold
T_SWDO_valid SWDCK low to SWDIO output valid
T_SWDO_hold SWDIO output hold after SWDCK high T = 1/f_SWDCK
Notes
52. Based on device characterization (Not production tested).
53. f_TCK must also be no more than 1/3 CPU clock frequency.
54. f_SWDCK must also be no more than 1/3 CPU clock frequency.
Parameter
Parameter
Parameter
Parameter
TDI setup before TCK high
TDI, TMS hold after TCK high
TDO hold after TCK high
TCK to device outputs valid
SWDCLK frequency
SWDIO input hold after SWDCK high
SWV mode SWV bit rate
TCK frequency
TMS setup before TCK high
TCK low to TDO valid
Delay from interrupt signal input to ISR
code execution from ISR code
Description
Description
Description
Description
PRELIMINARY
[52]
[52]
[52]
3.3 V ≤ V
1.71 V ≤ V
T = 1/f_TCK
T = 1/f_TCK
T = 1/f_TCK
3.3 V ≤ V
1.71 V ≤ V
1.71 V ≤ V
SWD over USBIO pins
T = 1/f_SWDCK
T = 1/f_SWDCK
Includes worse case completion of
longest instruction DIV with 6
cycles
DDD
DDD
DDD
DDD
DDD
Conditions
Conditions
Conditions
Conditions
PSoC
≤ 5 V
≤ 5 V
< 3.3 V
< 3.3 V
< 3.3 V,
®
3: CY8C36 Family Datasheet
(T/10) – 5
2T/5
Min
Min
2T/5
Min
T/4
T/4
T/4
Min
T/4
T/4
T/4
–
–
–
–
–
–
–
–
Typ
Typ
Typ
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
5.5
14
14
2T/5
25
Max
7
Max
7
Max
[53]
–
–
–
–
–
[54]
–
–
–
–
[53]
[54]
33
[54]
Page 95 of 111
Tcy CPU
Units
Units
Units
MHz
MHz
MHz
MHz
MHz
Units
Mbit
ns
–
–
–
–
[+] Feedback
[+] Feedback