CY8C3665AXI-010 Cypress Semiconductor Corp, CY8C3665AXI-010 Datasheet - Page 25

• Manufacturer Part Number: CY8C3665AXI-010
• Description: PSOC3
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C36xxr

Specifications of CY8C3665AXI-010

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 67MHz
• Number Of I /o: 62
• Eeprom Size: 1K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 32KB (32K x 8)
• Data Converters: A/D 2x12b, D/A 4x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: TQFP
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Rad Hardened: No
• Processor Series: CY8C36
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 67 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 0.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 62
• Eeprom Memory Size: 1KB
• Ram Memory Size: 4KB
• Cpu Speed: 67MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.1 Power Modes
PSoC 3 devices have four different power modes, as shown in
Table 6-1
easily provide required functionality and processing power while
simultaneously minimizing power consumption and maximizing
battery life in low-power and portable devices.
PSoC 3 power modes, in order of decreasing power
consumption are:
Table 6-1. Power Modes
Table 6-2. Power Modes Wakeup Time and Power Consumption
Document Number: 001-53413 Rev. *J
Active
Alternate
Active
Sleep
Hibernate
Note
Active
Alternate
Active
Sleep
Hibernate
16. Bus clock off. Execute from CPU instruction buffer at 6 MHz. See
Active
Alternate Active
Sleep
Hibernate
Modes
Modes
Power
Sleep
and
Primary mode of operation, all periph-
erals available (programmable)
Similar to Active mode, and is typically
configured to have fewer peripherals
active to reduce power. One possible
configuration is to use the UDBs for
processing, with the CPU turned off
All subsystems automatically disabled Manual register
All subsystems automatically disabled
Lowest power consuming mode with
all peripherals and internal regulators
disabled, except hibernate regulator is
enabled
Configuration and memory contents
retained
Wakeup
<100 µs
<15 µs
Table
Time
–
–
6-2. The power modes allow a design to
1.2 mA
Description
Current
200 nA
(Typ)
1 µA
–
[16]
Execution
defined
Code
User
Yes
No
No
PRELIMINARY
Wakeup, reset,
manual register
entry
Manual register
entry
entry
Manual register
entry
Entry Condition
Resources
Digital
None
I
All
All
Table 11-2
2
C
on page 59.
Comparator
Resources
Analog
Active is the main processing mode. Its functionality is
configurable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and RTC functionality.
The lowest power mode is hibernate, which retains register and
SRAM state, but no clocks, and allows wakeup only from I/O
pins.
power modes.
.
None
Any interrupt Any
Any interrupt Any
Comparator,
PICU, I
RTC, CTW,
LVD
PICU
All
All
PSoC
Wakeup
Source
Figure 6-5
2
C,
Clock Sources
ILO/kHzECO
®
Available
(programmable)
(programmable)
ILO/kHzECO
–
3: CY8C36 Family Datasheet
None
illustrates the allowable transitions between
Active Clocks
All
All
Wakeup Sources
PICU, I
Comparator,
CTW, LVD
All regulators available. Digital
and analog regulators can be
disabled if external regulation
used.
All regulators available. Digital
and analog regulators can be
disabled if external regulation
used.
Both digital and analog
regulators buzzed.
Digital and analog regulators
can be disabled if external
regulation used.
Only hibernate regulator active.
PICU
2
–
–
C, RTC,
Regulator
XRES, LVD,
Sources
Page 25 of 111
Reset
XRES
WDR
All
All
[+] Feedback
[+] Feedback