CY8C3665AXI-010 Cypress Semiconductor Corp, CY8C3665AXI-010 Datasheet - Page 20

• Manufacturer Part Number: CY8C3665AXI-010
• Description: PSOC3
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C36xxr

Specifications of CY8C3665AXI-010

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 67MHz
• Number Of I /o: 62
• Eeprom Size: 1K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 32KB (32K x 8)
• Data Converters: A/D 2x12b, D/A 4x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: TQFP
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Rad Hardened: No
• Processor Series: CY8C36
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 67 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 0.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 62
• Eeprom Memory Size: 1KB
• Ram Memory Size: 4KB
• Cpu Speed: 67MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.6.3 SFRs
The special function register (SFR) space provides access to frequently accessed registers. The memory map for the SFR memory
space is shown in
Table 5-2. SFR Map
The CY8C36 family provides the standard set of registers found
on industry standard 8051 devices. In addition, the CY8C36
devices add SFRs to provide direct access to the I/O ports on the
device. The following sections describe the SFRs added to the
CY8C36 family.
XData Space Access SFRs
The 8051 core features dual DPTR registers for faster data
transfer operations. The data pointer select SFR, DPS, selects
which data pointer register, DPTR0 or DPTR1, is used for the
following instructions:
The extended data pointer SFRs, DPX0, DPX1, MXAX, and
P2AX, hold the most significant parts of memory addresses
during access to the xdata space. These SFRs are used only
with the MOVX instructions.
During a MOVX instruction using the DPTR0/DPTR1 register,
the most significant byte of the address is always equal to the
contents of DPX0/DPX1.
Document Number: 001-53413 Rev. *J
Address
MOVX @DPTR, A
MOVX A, @DPTR
MOVC A, @A+DPTR
JMP @A+DPTR
INC DPTR
MOV DPTR, #data16
0×D8
0×D0
0×C8
0×C0
0×F8
0×F0
0×E8
0×E0
0×B8
0×B0
0×A8
0×A0
0×98
0×90
0×88
0×80
SFRPRT15DR
B
SFRPRT12DR
ACC
SFRPRT6DR
PSW
SFRPRT5DR
SFRPRT4DR
–
SFRPRT3DR
IE
P2AX
SFRPRT2DR
SFRPRT1DR
–
SFRPRT0DR
Table
0/8
5-2.
SFRPRT15PS
–
SFRPRT12PS
–
SFRPRT6PS
–
SFRPRT5PS
SFRPRT4PS
–
SFRPRT3PS
–
–
SFRPRT2PS
SFRPRT1PS
SFRPRT0PS
SP
1/9
PRELIMINARY
SFRPRT15SEL
SFRPRT12SEL
MXAX
–
SFRPRT6SEL
–
SFRPRT5SEL
SFRPRT4SEL
–
SFRPRT3SEL
–
SFRPRT1SEL
SFRPRT2SEL
–
SFRPRT0SEL
DPL0
2/A
During a MOVX instruction using the R0 or R1 register, the most
significant byte of the address is always equal to the contents of
MXAX, and the next most significant byte is always equal to the
contents of P2AX.
I/O Port SFRs
The I/O ports provide digital input sensing, output drive, pin
interrupts, connectivity for analog inputs and outputs, LCD, and
access to peripherals through the DSI. Full information on I/O
ports is found in
I/O ports are linked to the CPU through the PHUB and are also
available in the SFRs. Using the SFRs allows faster access to a
limited set of I/O port registers, while using the PHUB allows boot
configuration and access to all I/O port registers.
Each SFR supported I/O port provides three SFRs:
–
–
–
–
–
–
–
–
–
–
–
–
–
DPX0
–
DPH0
SFRPRTxDR sets the output data state of the port (where × is
port number and includes ports 0–6, 12 and 15).
The SFRPRTxSEL selects whether the PHUB PRTxDR
register or the SFRPRTxDR controls each pin’s output buffer
within the port. If a SFRPRTxSEL[y] bit is high, the
corresponding SFRPRTxDR[y] bit sets the output state for that
pin. If a SFRPRTxSEL[y] bit is low, the corresponding
PRTxDR[y] bit sets the output state of the pin (where y varies
from 0 to 7).
The SFRPRTxPS is a read only register that contains pin state
values of the port pins.
PSoC
3/B
®
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DPL1
3: CY8C36 Family Datasheet
I/O System and Routing
4/C
–
–
–
–
–
–
–
–
–
–
–
–
–
DPX1
–
DPH1
5/D
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DPS
on page 28.
6/E
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 20 of 111
7/F
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