CYII4SC014KAA-GTC Cypress Semiconductor Corp, CYII4SC014KAA-GTC Datasheet - Page 9

• Manufacturer Part Number: CYII4SC014KAA-GTC
• Description: IC SENSOR IMAGE COLOR 49-PGA
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII4SC014KAA-GTC

• Package / Case: 49-PGA
• Pixel Size: 8µm x 8µm
• Active Pixel Array: 3048H x 4560V
• Frames Per Second: 3
• Voltage - Supply: 3.3V
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: 0 C
• Image Size: 4560 H x 3048 V
• Color Sensing: Color
• Package: 49PGA
• Operating Temperature: 0 to 50 °C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: IBIS4-14000-C; IBIS4-14000-C

Table 4. Timing Constraints for the Row Sequencer
Notes CLK = one clock period of the master clock, shortest system time period available.
Document #: 38-05709 Rev. *D
Symbol
m
a
b
d
e
g
h
c
k
f
i
j
l
CLOCK_YL
SYNC_YR
SYNC_YL
SELECT
RESET
SHR
SHS
SYL
SYR
PC
h+2*CLK
200 ns
Min
a
k
1.28 μ s
600 ns
100 ns
500 ns
240 ns
Optional reset pulse
2.7 μ s
1.3 μ s
6.5 μ s
1.4 μ s
500ns
10 μ s
Typ.
5 μ s
l
3 μ s
for reset black
h
b
Min. SYNC set-up times. SYNC_Y is clocked in on rising edge on CLK_Y. SYNC_Y pulse
must overlap CLK_Y by one clock period. Setup times of 200 ns apply after SYNC edges.
Within this setup time no rising CLK edge may occur.
Duration of PC pulse.
Delay between falling edge on PC and rising edge on SHS/SHR. Duration of SHS/SHR
pulse.
Delay between rising edge on PC and rising edge on SELECT.
Delay between rising edge on SELECT and rising edge on SHS/SHR.
Delay between rising edge on SHS and falling edge on SELECT.
Delay between falling edge of SELECT and rising edge of RESET.
Duration of RESET pulse.
Delay between rising edge on SHR and rising edge on SYR.
SYL and SYR pulses must overlap second RESET pulse at both sides by one clock cycle.
Duration of CLOCK_Y pulse.
Delay between falling edge of CLK_Y and Falling edge of PC and SHS.
Delay between falling edge of RESET and falling edge of PC and SHR.
d
c
e
f
Figure 9. Line Read Out Timing
g
h
m
b
c
d
e
Description
f
i
Only when the electronic
j
shutter is used
CYII4SM014KAA-GEC
h
CYII4SC014KAA-GTC
j
Once each
For each
new row
frame
Page 9 of 27
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