ISPPAC-CLK5610V-01T48C Lattice, ISPPAC-CLK5610V-01T48C Datasheet
ISPPAC-CLK5610V-01T48C
Specifications of ISPPAC-CLK5610V-01T48C
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ISPPAC-CLK5610V-01T48C Summary of contents
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... Input Available only on ispClock5620 © 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Lattice Semiconductor General Description and Overview The ispClock5610 and ispClock5620 are in-system-programmable high-fanout PLL-based clock drivers designed for use in high performance communications and computing applications. The ispClock5610 provides sin- gle-ended or five differential clock outputs, while the ispClock5620 provides single-ended or 10 differential clock outputs. Each pair of outputs may be independently confi ...
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... Lattice Semiconductor Figure 2. ispClock5620 Functional Block Diagram PS0 PS1 Profile Select Control REFSEL REFA+ INPUT REFA- DIVIDER 0 M REFVTT (1-32) 1 REFB+ REFB- FEEDBACK N DIVIDER (1-32) FBKSEL FBKA FBKA- 0 FBKVTT 1 FBKB+ FBKB- LOCK RESET PLL_BYPASS SGATE GOE OUTPUT ENABLE CONTROLS LOCK DETECT ...
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... Lattice Semiconductor Absolute Maximum Ratings Core Supply Voltage -0.5 to 5.5V CCD PLL Supply Voltage -0.5 to 5.5V CCA JTAG Supply Voltage -0.5 to 5.5V CCJ Output Driver Supply Voltage V CCO Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V 1 Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C Junction Temperature with power supplied . . . . . . . . . . . . . . . . . . . -40 to 130° ...
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... Lattice Semiconductor 2 E CMOS Memory Write/Erase Characteristics Parameter Erase/Reprogram Cycles Performance Characteristics – Power Supply Symbol Parameter I Core Supply Current CCD I Analog Supply Current CCA Output Driver Supply Current I CCO (per Bank) I JTAG I/O Supply Current (static) CCJ 1. Supply current consumed by each bank, both outputs active, 18pF load, 320MHz output frequency. ...
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... Lattice Semiconductor DC Electrical Characteristics – Differential LVPECL Symbol Parameter V Input Voltage High IH V Input Voltage Low Output High Voltage Output Low Voltage OL 1. 100Ω differential termination. DC Electrical Characteristics – Input/Output Loading Symbol Parameter I Input Leakage LK I Input Pull-up Current PU I Input Pull-down Current ...
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... Lattice Semiconductor Switching Characteristics – Timing Adders for I/O Modes Adder Type 2 t Input Adders IOI LVTTL_in Using LVTTL Standard LVCMOS18_in Using LVCMOS 1.8V Standard LVCMOS25_in Using LVCMOS 2.5V Standard LVCMOS33_in Using LVCMOS 3.3V Standard SSTL2_in Using SSTL2 Standard SSTL3_in Using SSTL3 Standard ...
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... Lattice Semiconductor Output Test Loads Figures 3-5 show the equivalent termination loads used to measure rise/fall times, output timing adders and other selected parameters as noted in the various tables of this data sheet. Figure 3. CMOS Termination Load ispCLOCK Zo = 50Ω Figure 4. HSTL/SSTL Termination Load ispCLOCK Zo = HSTL: ~20Ω ...
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... Lattice Semiconductor Programmable Input and Output Termination Characteristics Symbol Parameter R Input Resistance Output Resistance OUT 1. Guaranteed by characterization. Conditions V Voltage CCO Rin=40Ω setting Rin=45Ω setting Rin=50Ω setting Rin=55Ω setting Rin=60Ω setting Rin=65Ω setting Rin=70Ω setting VCCO=3 ...
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... Lattice Semiconductor Performance Characteristics – PLL Symbol Parameter Reference and feedback input f f REF, FBK frequency range t Reference and feedback input CLOCKHI, t clock HIGH and LOW times CLOCKLO t Reference and feedback input RINP, t rise and fall times FINP M M-divider range DIV ...
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... Lattice Semiconductor Timing Specifications Skew Matching Symbol Parameter t Output-output Skew SKEW Programmable Skew Control Symbol Parameter t Skew Control Range SKRANGE SK Skew Steps per range STEPS 2 t Skew Step Size SKSTEP 3 t Skew Time Error SKERR 1. Skew control range is a function of VCO frequency (f ...
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... Lattice Semiconductor Timing Specifications (Cont.) Boundary Scan Logic Symbol t TCK (BSCAN Test) Clock Cycle BTCP t TCK (BSCAN Test) Pulse Width High BTCH t TCK (BSCAN Test) Pulse Width Low BTCL t TCK (BSCAN Test) Setup Time BTSU t TCK (BSCAN Test) Hold Time ...
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... Lattice Semiconductor Timing Diagrams Figure 7. Erase (User Erase or Erase All) Timing Diagram VIH TMS VIL SU1 SU1 CKH GKL VIH TCK VIL State Update-IR Run-Test/Idle (Erase) Figure 8. Programming Timing Diagram VIH TMS VIL SU1 H t CKH VIH TCK VIL State Update-IR Figure 9 ...
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... Lattice Semiconductor Typical Performance Characteristics I vs. f CCD (Normalized to 640MHz) 1.2 1 0.8 0.6 0.4 0.2 0 300 400 500 f (MHz) VCO Typical Skew Error vs. Setting (Skew Mode = FINE, f 100 -25 -50 -75 -100 Skew Setting # Cycle-Cycle Jitter vs. VCO Frequency V 320 370 420 470 VCO Frequency (MHz) ...
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... Lattice Semiconductor Typical Performance Characteristics (Cont.) Typical Phase Jitter vs. VCO Frequency PFD MHz 16 320 370 420 470 VCO Frequency Typical Period Jitter vs. VCO Frequency PFD = 80 MHz 320 370 420 470 VCO Frequency *PFD = Phase/Frequency Detector Detailed Description PLL Subsystem The ispClock5600 provides an integral phase-locked-loop (PLL) which may be used to generate output clock sig- nals at lower, higher, or the same frequency as a user-supplied input reference signal. The core functions of the PLL are an edge-sensitive phase detector, a programmable loop fi ...
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... LOCK signal is asserted when the frequencies of the feedback and reference signals match. The option of which mode to use is programmable and may be set using PAC-Designer software (available from the Lattice web site at www.latticesemi.com). In phase-lock mode the lock detector asserts the LOCK signal as soon as a lock condition is determined. In fre- quency-lock mode, however, the PLL must locked condition for a set number of phase detector cycles before the LOCK signal will be asserted ...
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... Lattice Semiconductor Table 2. Filter Settings for Minimizing Cycle-Cycle and Period Jitter Table 3. Filter Settings for Optimizing Overall Jitter (Recommended) Note that the choice of loop filter parameters can have significant effects on settling time, output jitter, and whether the PLL will be fundamentally stable and be able to lock to an incoming signal. The values recommended in Table 2 and Table 3 were chosen to provide maximum loop stability while still providing exceptional jitter performance. Please note that when the skew mode is set to ‘ ...
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... Lattice Semiconductor Figure 12. PLL Loop Bandwidth vs. Feedback Divider Setting (nominal) VCO The ispClock5600 provides an internal VCO which provides an output frequency ranging from 320MHz to 640MHz. The VCO is implemented using differential circuit design techniques which minimize the influence of power supply noise on measured output jitter. The VCO is also used to generate skews as a function of the total VCO period. ...
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... Lattice Semiconductor Because the VCO has an operating frequency range spanning 320 MHz to 640 MHz, and the V dividers provide division ratios from 2 to 64, the ispClock5600 can generate output signals ranging from 5MHz to 320 MHz. For per- formance and stability reasons, however, there are several constraints which should be followed when selecting divider values: • ...
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... Lattice Semiconductor halved, so that they provide division ratios ranging from 1 to 32. The output frequency for a given V divider (f be determined by Please note that PLL_BYPASS mode is provided primarily for testing purposes. When PLL_BYPASS mode is enabled, features such as lock detect and skew generation are unavailable. ...
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... Lattice Semiconductor Figure 13. ispClock5600 Clock Reference and Feedback Input Structure (REFA+/- Pair Shown) ispClock5600 REFA+ REFA REFVTT The following usage guidelines are suggested for interfacing to supported logic families. LVTTL (3.3V), LVCMOS (1.8V, 2.5V, 3.3V) The receiver should be set to LVCMOS or LVTTL mode, and the input signal should be connected to the ‘+’ termi- nal of the input pair (e.g. REFA+). The ‘ ...
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... Lattice Semiconductor One important point to note is that the termination supplies must have low impedance and be able to both source and sink current without experiencing fluctuations. These requirements generally preclude the use of a resistive divider network, which has an impedance comparable to the resistors used commodity-type linear voltage regulators, which can only source current. The best way to develop the necessary termination voltages is with a regulator specifi ...
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... Lattice Semiconductor Differential HSTL and SSTL HSTL and SSTL are sometimes used in a differential form, especially for distributing clocks in high-speed memory systems. Figure 16 shows how ispClock5600 reference input should be configured for accepting these standards. The major difference between differential and single-ended forms of these logic standards is that in the differential case, the REFA- input is used as a signal input, not a reference level, and that both terminating resistors are engaged and set to 50Ω ...
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... Lattice Semiconductor Note that while a floating 100Ω resistor forms a complete termination for an LVDS signal line, additional circuitry may be required to satisfactorily terminate a differential LVPECL signal. This is because a true bipolar LVPECL out- put driver typically requires an external DC ‘pull-down’ path properly bias its open emitter output stage. When interfacing to an LVPECL input signal, the ispClock5600’s inter- nal termination resistors should not be used for this pull-down function, as they may be damaged from excessive current ...
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... Lattice Semiconductor In the case where an output bank is unused, the associated VCCO pin may be either left floating or tied to ground to reduce quiescent power consumption. We recommend, however, that all unused VCCO pins be tied to ground where possible. All GND0 pins must be tied to ground, regardless of whether or not the associated bank is used. ...
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... Lattice Semiconductor end, the ispClock5600’s internal termination resistors are not available in these modes. Also note that output slew- rate control is not available in LVDS or LVPECL mode, and that these drivers always operate at a fixed slew-rate. Polarity control (true/inverted) is available for all output drivers. In the case of single-ended output standards, the polarity of each of the two output signals from each bank may be controlled independently ...
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... In applications where a majority of the ispClock5610 or ispClock5620’s outputs are active and operating at or near maximum output frequency (320 MHz), package thermal limitations may need to be considered to ensure a suc- cessful design. Thermal characteristics of the packages employed by Lattice Semiconductor may be found in the document Thermal Management which may be obtained at www.latticesemi.com. ...
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... Lattice Semiconductor Figure 23. Maximum Ambient Temperature vs. Number of Active Output Banks Temperature Derating Curves (Outputs LVCMOS 3.3V Active Output Banks (a) Temperature Derating Curves (Outputs LVDS Active Output Banks Figure 23b shows another derating curve, derived under the assumption that the output frequency is 100MHz. For many applications, 100MHz outputs will be a more realistic scenario. Comparing the maximum temperature limits of Figure 23b with Figure 23a, one can see that signifi ...
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... Lattice Semiconductor sumption by turning off unused drivers, these features can also be used for functional testing purposes. The follow- ing inputs pins are used for output enable functions: • GOE – global output enable • OEX, OEY – secondary output enable controls • ...
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... Lattice Semiconductor Unlike the skew adjustment features provided in many competing products, the ispClock5600’s skew adjustment feature provides exact and repeatable delays which exhibit extremely low channel-to-channel and device-to-device variation. This is achieved by deriving all skew timing from the VCO, which results in the skew increment being a lin- ear function of the VCO period. For this reason, skews are defi ...
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... Lattice Semiconductor remain unchanged from what they were in fine mode. One drawback of moving from fine skew mode into coarse skew mode is that it may not be possible to maintain consistent output frequencies, as only those V-divider settings which are multiples of four (in fine mode) may be divided by two. For example, a V-divider setting of 24 will divide down to 12, which is also a legal V-divider setting, whereas an initial setting of 26 would divide down to 13, which is not a valid setting ...
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... Lattice Semiconductor Figure 26. Output Timing Adders for Logic Type (a) and Output Slew Rate (b) LVPECL Output ( IOS LVTTL Output (T = 0.1ns) IOS Similarly, when one changes the slew rate of an output, the output slew rate adders (t the resulting skew. In this case, the fastest slew setting (1) is used as the baseline against which other slews are measured. For example, in the case of outputs confi ...
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... Lattice Semiconductor Profile Select The ispClock5600 stores all internal configuration data in on-board E figuration profiles may be stored in each device. The choice of which configuration profi active is specified thought the profile select inputs PS0 and PS1, as shown in Table 8. ...
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... Full device programming is supported using PC parallel port I/O operations and a download cable connected to the serial programming interface pins of the ispClock5600. A library of configurations is included with basic solutions and examples of advanced circuit techniques are available on the Lattice web site at www.latticesemi.com. In addi- tion, comprehensive on-line and printed documentation is provided that covers all aspects of PAC-Designer operation. ...
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... Evaluation Fixture Included in the basic ispClock5600 Design Kit is an engineering prototype board that can be connected to the par- allel port using a Lattice ispDOWNLOAD ispClock5600 and can be used in real time to check circuit operation as part of the design process. Input and out- put connections (SMA connectors for all RF signals) are provided to aid in the evaluation of the ispClock5600 for a given application ...
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... Lattice Semiconductor IEEE Standard 1149.1 Interface (JTAG) Serial Port Programming Interface Communication with the ispClock5600 is facilitated via an IEEE 1149.1 test access port (TAP used by the ispClock5600 both as a serial programming interface, and for boundary scan test purposes. A brief description of the ispClock5600 JTAG interface follows. For complete details of the reference specifi ...
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... Lattice Semiconductor Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-Register. But there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on default state ...
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... The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (111111). The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI and TDO. The bit code for this instruction is defined by Lattice as shown in Table 9. The EXTEST (external test) instruction is required and will place the device into an external boundary test mode while also enabling the boundary scan register to be connected between TDI and TDO. The bit code of this instruc- tion is defi ...
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... E Configured In addition to the four instructions described above, there are 20 unique instructions specified by Lattice for the ispClock5620. These instructions are primarily used to interface to the various user registers and the E volatile memory. Additional instructions are used to control or monitor other features of the device, including bound- ary scan operations ...
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... Lattice Semiconductor VERIFY – This instruction loads data from the E shifted out. The device must already be in programming mode for this instruction to execute. VERIFY_INCR – This instruction copies the E umn register and then auto-increments the value of the address register. The device must already be in program- ming mode for this instruction to execute. DISCHARGE – ...
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... Lattice Semiconductor Pin Descriptions Pin Name Description VCCO_0 Output Driver ‘0’ VCC VCCO_1 Output Driver ‘1’ VCC VCCO_2 Output Driver ‘2’ VCC VCCO_3 Output Driver ‘3’ VCC VCCO_4 Output Driver ‘4’ VCC VCCO_5 Output Driver ‘5’ VCC VCCO_6 Output Driver ‘ ...
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... Lattice Semiconductor Pin Descriptions (Continued) Pin Name Description VCCD Digital Core VCC GNDD Digital GND VCCJ JTAG interface VCC REFA+ Clock Reference A positive input REFA- Clock Reference A negative input REFB+ Clock Reference B positive input REFB- Clock Reference B negative input REFSEL Clock Reference Select input (LVCMOS) ...
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... Lattice Semiconductor Detailed Pin Descriptions VCCO_[0..9], GNDO_[0..9] – These pins provide power and ground for each of the output banks. In the case when an output bank is unused, its corresponding VCCO pin may be left unconnected or preferably should be tied to ground. ALL GNDO pins should be tied to ground regardless of whether the associated bank is used or not. When a bank is used, it should be individually bypassed with a capacitor in the range of 0 ...
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... Lattice Semiconductor GOE – Global output enable. This pin drives all outputs to a high-impedance state when it is pulled HIGH. GOE also controls the internal feedback buffer, so that bringing GOE high will cause the PLL to lose lock. PS0, PS1 – These input pins are used to select one of four user-defined configuration profiles for the device. ...
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... Lattice Semiconductor Package Diagrams 48-Pin TQFP (Dimensions in Millimeters) PIN 1 INDICATOR 0. SECTION NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982. 2. ALL DIMENSIONS ARE IN MILLIMETERS. DATUMS A, B AND DETERMINED AT DATUM PLANE DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.254 AND E1 DIMENSIONS ...
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... Lattice Semiconductor 100-Pin TQFP (Dimensions in Millimeters) PIN 1 INDICATOR TOP VIEW SIDE VIEW SECTION B-B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982. 2. ALL DIMENSIONS ARE IN MILLIMETERS. DATUMS A, B AND DETERMINED AT DATUM PLANE DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.254 AND E1 DIMENSIONS ...
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... Lattice Semiconductor Part Number Description ispPAC-CLK56XX XXXX X Device Family Device Number CLK5610 CLK5620 Ordering Information Conventional Packaging Part Number ispPAC-CLK5610V-01T48C ispPAC-CLK5620V-01T100C Part Number ispPAC-CLK5610V-01T48I ispPAC-CLK5620V-01T100I Lead-Free Packaging Part Number ispPAC-CLK5610V-01TN48C ispPAC-CLK5620V-01TN100C Part Number ispPAC-CLK5610V-01TN48I ispPAC-CLK5620V-01TN100I Commercial Clock Outputs Supply Voltage 10 3. ...
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... Lattice Semiconductor Package Options ispClock5610: 48-pin TQFP VCCO_0 BANK_0B BANK_0A GNDO_0 VCCO_1 BANK_1B BANK_1A GNDO_1 VCCO_2 BANK_2B BANK_2A GNDO_2 ispPAC CLK5610V-01T48C ispClock5600 Family Data Sheet 36 VCCJ 35 TDO 34 LOCK 33 VCCD 32 GNDO_4 31 BANK_4A 30 BANK_4B 29 VCCO_4 28 GNDO_3 27 BANK_3A 26 BANK_3B 25 VCCO_3 ...
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... BANK_1B 8 BANK_1A 9 GNDO_1 10 VCCO_2 11 BANK_2B 12 BANK_2A 13 GNDO_2 14 VCCO_3 15 BANK_3B 16 BANK_3A 17 GNDO_3 18 VCCO_4 19 BANK_4B 20 BANK_4A 21 GNDO_4 22 n/c 23 n/c 24 n/c 25 ispClock5600 Family Data Sheet ispPAC-CLK5620V-01T100C 49 75 n/c 74 VCCJ 73 TDO 72 LOCK 71 VCCD 70 GNDO_9 69 BANK_9A 68 BANK_9B 67 VCCO_9 66 GNDO_8 65 BANK_8A 64 BANK_8B 63 VCCO_8 62 GNDO_7 61 BANK_7A 60 BANK_7B 59 VCCO_7 58 ...