ISPPAC-CLK5610V-01T48C Lattice, ISPPAC-CLK5610V-01T48C Datasheet - Page 10

• Manufacturer Part Number: ISPPAC-CLK5610V-01T48C
• Description: Clock Drivers & Distribution 3.3V 10-320MHz
• Manufacturer: Lattice

Specifications of ISPPAC-CLK5610V-01T48C

• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Performance Characteristics – PLL
f
t
t
t
t
M
N
f
f
V
f
t
t
t
tφ
t
DC
t
t
PSR
1. In PLL Bypass mode (PLL_BYPASS = HIGH), output will support frequencies down to 0Hz (divider chain is a fully static design).
2. Dividers should be set so that they provide the phase detector with signals of 10MHz or greater for loop stability.
3. f
4. Variation in duty cycle expressed in ps. To obtain duty cycle percentage error (%
5. See Figures 3-5 for output loads.
6. milli-Unit Interval
7. Input and outputs LVPECL mode
8. f
REF,
CLOCKHI,
CLOCKLO
RINP,
FINP
PFD
VCO
OUT
JIT
JIT
JIT(
DELAY
PDBYPASS
L
DIV
DIV
DIV
Symbol
f
ERR
IN
OUT
IN
(cc)
(per)
φ
)
f
= f
= 100MHz, M = 1, N = 3, V = 2, output type LVPECL.
FBK
x DC
OUT
= 100 MHz, M = N = 1, V = 6, output type LVPECL.
ERR.
Reference and feedback input
frequency range
Reference and feedback input
clock HIGH and LOW times
Reference and feedback input
rise and fall times
M-divider range
N-Divider range
Phase detector input frequency
range
VCO operating frequency
Output Divider range
Output frequency range
Output adjacent-cycle jitter
(1000 cycle sample)
Output period jitter
(10000 cycle sample)
Reference clock to output jitter
(6000 cycle sample)
Static phase offset
Reference clock to output delay Internal feedback mode
Output duty cycle error (see
Table 4 for nominal values)
Reference clock to output
propagation delay
PLL Lock time
Power supply rejection, period
jitter vs. power supply noise
2
Parameter
1
4
Measured between 20% and 80%
levels
Even integer values only
Fine Skew Mode,
f
Coarse Skew Mode,
f
Loop filter from Table 2
Loop filter from Table 3
Loop filter from Table 2
Loop filter from Table 3
Loop filter from Table 2
Loop filter from Table 3
PFD input frequency ≥100MHz
PFD input frequency <100MHz
Output type LVDS, V
Output type LVCMOS 3.3V
f
M=1, V=2
From Power-up event
From Reset event
f
VCCA = VCCD = VCCO modulated
with 100kHz sinusoidal stimulus
VCO
VCO
OUT
IN
= f
= 640MHz
>100 MHz
= 640MHz
OUT
= 100MHz
Conditions
10
CCO
3
8
3
8
3
8
7
= 3.3V
ERR
5
) for a given output frequency (f
7
7
5
ispClock5600 Family Data Sheet
-37.5
Min.
1.25
-375
320
0.3
10
10
10
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
2
5
Typ.
0.45
0.05
150
NA
-75
—
—
—
—
—
—
—
—
—
45
45
38
—
—
—
15
—
8
9
6
Max.
22.5
320
320
640
320
160
225
260
300
500
NA
0.6
32
32
64
60
70
10
12
50
50
—
—
—
OUT
5
), %
ERR
ps (RMS)
ps (RMS)
ps (RMS)
ps (RMS)
ps(RMS)
mV(p-p)
ps (p-p)
ps (p-p)
Units
mUI
MHz
MHz
MHz
MHz
MHz
= 100 x
ns
ns
ps
ns
ps
ps
ns
µs
µs
6