ISPPAC-CLK5610V-01T48C Lattice, ISPPAC-CLK5610V-01T48C Datasheet - Page 21

Clock Drivers & Distribution 3.3V 10-320MHz

ISPPAC-CLK5610V-01T48C

Manufacturer Part Number
ISPPAC-CLK5610V-01T48C
Description
Clock Drivers & Distribution 3.3V 10-320MHz
Manufacturer
Lattice

Specifications of ISPPAC-CLK5610V-01T48C

Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Maximum Operating Temperature
70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISPPAC-CLK5610V-01T48C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Figure 13. ispClock5600 Clock Reference and Feedback Input Structure (REFA+/- Pair Shown)
The following usage guidelines are suggested for interfacing to supported logic families.
LVTTL (3.3V), LVCMOS (1.8V, 2.5V, 3.3V)
The receiver should be set to LVCMOS or LVTTL mode, and the input signal should be connected to the ‘+’ termi-
nal of the input pair (e.g. REFA+). The ‘-’ input terminal should be left floating. CMOS transmission lines are gener-
ally source terminated, so all termination resistors should be set to the OPEN state. Figure 14 shows the proper
configuration. Please note that because switching thresholds are different for LVCMOS running at 1.8V, there is a
separate configuration setting for this particular standard.
Figure 14. LVCMOS/LVTTL Input Receiver Configuration
HSTL, SSTL2, SSTL3
The receiver should be set to HSTL/SSTL mode, and the input signal should be fed into the ‘+’ terminal of the input
pair. The ‘-’ input terminal should be tied to the appropriate V
terminal should be tied to a V
set to 50Ω. Figure 15 shows an appropriate configuration. Refer to the “Recommended Operating Conditions -
Supported Logic Standards” table in this data sheet for suitable values of V
REFVTT
REFA+
REFA-
ispClock5600
TT
R
T
Signal In
termination supply. The positive input’s terminating resistor should be engaged and
No Connect
No Connect
REFVTT
REFA+
REFA-
R
T
ispClock5600
R
T
OPEN
Single-ended
Differential
21
Receiver
Receiver
REF
value, and the associated REFVTT or FBKVTT
ispClock5600 Family Data Sheet
Single-ended
Receiver
REF
and V
To Internal
Logic
TT.

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