RFD14N05SM9A Fairchild Semiconductor, RFD14N05SM9A Datasheet - Page 5

MOSFET N-CH 50V 14A DPAK

RFD14N05SM9A

Manufacturer Part Number
RFD14N05SM9A
Description
MOSFET N-CH 50V 14A DPAK
Manufacturer
Fairchild Semiconductor
Type
Power MOSFETr
Datasheet

Specifications of RFD14N05SM9A

Fet Type
MOSFET N-Channel, Metal Oxide
Fet Feature
Standard
Rds On (max) @ Id, Vgs
100 mOhm @ 14A, 10V
Drain To Source Voltage (vdss)
50V
Current - Continuous Drain (id) @ 25° C
14A
Vgs(th) (max) @ Id
4V @ 250µA
Gate Charge (qg) @ Vgs
40nC @ 20V
Input Capacitance (ciss) @ Vds
570pF @ 25V
Power - Max
48W
Mounting Type
Surface Mount
Package / Case
DPak, TO-252 (2 leads+tab), SC-63
Number Of Elements
1
Polarity
N
Channel Mode
Enhancement
Drain-source On-res
0.1Ohm
Drain-source On-volt
50V
Gate-source Voltage (max)
±20V
Drain Current (max)
14A
Power Dissipation
48W
Output Power (max)
Not RequiredW
Frequency (max)
Not RequiredMHz
Noise Figure
Not RequireddB
Power Gain
Not RequireddB
Drain Efficiency
Not Required%
Operating Temp Range
-55C to 175C
Operating Temperature Classification
Military
Mounting
Surface Mount
Pin Count
2 +Tab
Package Type
DPAK
Configuration
Single
Transistor Polarity
N-Channel
Resistance Drain-source Rds (on)
0.1 Ohms
Drain-source Breakdown Voltage
50 V
Gate-source Breakdown Voltage
+/- 20 V
Continuous Drain Current
14 A
Maximum Operating Temperature
+ 175 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 55 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
RFD14N05SM9A

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©2002 Fairchild Semiconductor Corporation
Typical Performance Curves
Test Circuits and Waveforms
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VARY t
REQUIRED PEAK I
0V
V
700
600
500
400
300
200
100
GS
0
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
0
P
FIGURE 16. SWITCHING TIME TEST CIRCUIT
TO OBTAIN
V
t
GS
P
V
5
AS
DS
, DRAIN TO SOURCE VOLTAGE (V)
C
C
C
ISS
OSS
RSS
V
GS
10
R
G
R
GS
15
V
DS
V
C
C
C
V
GS
I
ISS
RSS
OSS
Unless Otherwise Specified (Continued)
AS
DS
DUT
= 0V, f = 1MHz
R
= C
DUT
= C
≈ C
L
0.01Ω
20
L
GS
GD
DS
+ C
+ C
GD
+
-
GD
+
-
V
V
DD
DD
25
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260,
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
0
0
0
V
V
GS
60
45
30
15
DS
10%
0
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
V
t
d(ON)
90%
DD
20
CONSTANT CURRENT GATE DRIVE
50%
t
ON
= BV
I G REF
---------------------
I G ACT
10%
(
(
t
DSS
r
I
AS
)
)
R
I
V
PULSE WIDTH
G(REF)
0.75 BV
0.50 BV
0.25 BV
GS
L
t, TIME (µs)
t
= 3.57Ω
P
= 10V
RFD14N05, RFD14N05SM, RFP14N05 Rev. B
= 0.4mA
DSS
DSS
DSS
BV
t
AV
DSS
V
DD
80
= BV
I G REF
---------------------
I G ACT
t
d(OFF)
(
(
90%
DSS
V
t
OFF
DS
50%
)
)
t
f
10%
V
10
7.5
5.0
2.5
0
90%
DD

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