FQD5P20TM_F080 Fairchild Semiconductor, FQD5P20TM_F080 Datasheet

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FQD5P20TM_F080

Manufacturer Part Number
FQD5P20TM_F080
Description
MOSFET P-CH 200V 3.7A DPAK
Manufacturer
Fairchild Semiconductor
Series
QFET™r
Datasheet

Specifications of FQD5P20TM_F080

Fet Type
MOSFET P-Channel, Metal Oxide
Fet Feature
Standard
Rds On (max) @ Id, Vgs
1.4 Ohm @ 1.85A, 10V
Drain To Source Voltage (vdss)
200V
Current - Continuous Drain (id) @ 25° C
3.7A
Vgs(th) (max) @ Id
5V @ 250µA
Gate Charge (qg) @ Vgs
13nC @ 10V
Input Capacitance (ciss) @ Vds
430pF @ 25V
Power - Max
2.5W
Mounting Type
Surface Mount
Package / Case
DPak, TO-252 (2 leads+tab), SC-63
Configuration
Single
Transistor Polarity
P-Channel
Resistance Drain-source Rds (on)
1.4 Ohms
Forward Transconductance Gfs (max / Min)
2.2 S
Drain-source Breakdown Voltage
- 200 V
Gate-source Breakdown Voltage
+/- 30 V
Continuous Drain Current
- 3.7 A
Power Dissipation
2.5 W
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 55 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
©2008 Fairchild Semiconductor Internationa
FQD5P20 / FQU5P20
200V P-Channel MOSFET
General Description
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switching DC/DC converters.
Absolute Maximum Ratings
Thermal Characteristics
* When mounted on the minimum pad size recommended (PCB Mount)
V
I
I
V
E
I
E
dv/dt
P
T
T
R
R
R
D
DM
AR
J
L
Symbol
DSS
GSS
AS
AR
D
Symbol
, T
JC
JA
JA
STG
G
Drain-Source Voltage
Drain Current
Drain Current
Gate-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (T
Power Dissipation (T
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient *
Thermal Resistance, Junction-to-Ambient
S
FQD Series
D-PAK
D
- Continuous (T
- Continuous (T
- Pulsed
- Derate above 25°C
A
C
= 25°C) *
Parameter
= 25°C)
Parameter
G
T
D
C
C
C
= 25°C unless otherwise noted
S
= 25°C)
= 100°C)
(Note 1)
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Features
• -3.7A, -200V, R
• Low gate charge ( typical 10 nC)
• Low Crss ( typical 12 pF)
• Fast switching
• 100% avalanche tested
• RoHS Compliant
FQU Series
I-PAK
FQD5P20 / FQU5P20
Typ
--
--
--
DS(on)
-55 to +150
= 1.4
-2.34
-14.8
-200
0.36
-3.7
330
-3.7
-5.5
300
4.5
2.5
45
30
G
@V
! ! ! !
! ! ! !
Max
2.78
110
50
GS
October 2008
QFET
= -10 V
▶ ▶ ▶ ▶
▶ ▶ ▶ ▶
! ! ! !
! ! ! !
D
S
! ! ! !
! ! ! !
● ●
● ●
● ●
● ●
● ●
● ●
▲ ▲ ▲ ▲
▲ ▲ ▲ ▲
Rev. A1, October 2008
Units
W/°C
Units
°C/W
°C/W
°C/W
V/ns
mJ
mJ
°C
°C
W
W
V
A
A
A
V
A
®

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FQD5P20TM_F080 Summary of contents

Page 1

... Thermal Resistance, Junction-to-Ambient * JA R Thermal Resistance, Junction-to-Ambient JA * When mounted on the minimum pad size recommended (PCB Mount) ©2008 Fairchild Semiconductor Internationa Features • -3.7A, -200V, R • Low gate charge ( typical 10 nC) • Low Crss ( typical 12 pF) • Fast switching • 100% avalanche tested • ...

Page 2

... Repetitive Rating : Pulse width limited by maximum junction temperature 36.2mH -3.7A -50V ≤ -4.8A, di/dt ≤ 300A ≤ DSS, 4. Pulse Test : Pulse width ≤ 300 s, Duty cycle ≤ Essentially independent of operating temperature ©2008 Fairchild Semiconductor Internationa T = 25°C unless otherwise noted C Test Conditions -250 -250 A, Referenced to 25° -200 ...

Page 3

... Drain-Source Voltage [ 10V 2 20V GS 1.8 1.2 0.6 0 Drain Current [A] D 750 600 C 450 C 300 C 150 Drain-Source Voltage [V] DS Figure 1. On-Region Characteristics ©2008 Fairchild Semiconductor Internationa ※ Notes : 1. 250μ s Pulse Test 25℃ ※ Note : T = 25℃ 0 shorted) iss oss ds gd ...

Page 4

... Notes : 150 Single Pulse Drain-Source Voltage [V] DS Figure 9. Maximum Safe Operating Area ©2008 Fairchild Semiconductor Internationa (Continued) 2.5 2.0 1.5 1.0 ※ Notes : 0 -250 μ 0.0 100 150 200 -100 o C] Figure 8. On-Resistance Variation 4 3 100 Figure 10. Maximum Drain Current ※ ...

Page 5

... Resistive Switching Test Circuit & Waveforms -10V -10V Unclamped Inductive Switching Test Circuit & Waveforms -10V -10V ©2008 Fairchild Semiconductor Internationa Gate Charge Test Circuit & Waveform Same Type Same Type as DUT as DUT -10V -10V DUT DUT DUT DUT ...

Page 6

... Peak Diode Recovery dv/dt Test Circuit & Waveforms Driver ) ( Driver ) DUT ) ( DUT ) DUT ) ( DUT ) ©2008 Fairchild Semiconductor Internationa + + DUT DUT Driver Driver Compliment of DUT Compliment of DUT (N-Channel) (N-Channel) • dv/dt controlled by R • dv/dt controlled by R • I • I controlled by pulse period ...

Page 7

... Mechanical Dimensions ©2008 Fairchild Semiconductor Internationa D - PAK Dimensions in Millimeters Rev. A1, October 2008 ...

Page 8

... Mechanical Dimensions ©2008 Fairchild Semiconductor Internationa I - PAK Dimensions in Millimeters Rev. A1, October 2008 ...

Page 9

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. Build it Now™ CorePLUS™ CorePOWER™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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