LAN9311-NZW Standard Microsystem (Smsc), LAN9311-NZW Datasheet - Page 37
LAN9311-NZW
Manufacturer Part Number
LAN9311-NZW
Description
Ethernet Switch 2-Port 10Mbps/100Mbps 128-Pin XVTQFP
Manufacturer
Standard Microsystem (Smsc)
Datasheet
1.LAN9311-NU.pdf
(460 pages)
Specifications of LAN9311-NZW
Package
128XVTQFP
Phy/transceiver Interface
MII
Number Of Primary Switch Ports
2
Maximum Data Rate
100 Mbps
Internal Memory Buffer Size
32 KB
Vlan Support
Yes
Power Supply Type
Analog
Minimum Single Supply Voltage
3 V
Maximum Single Supply Voltage
3.6 V
Maximum Supply Current
0.295 A
Maximum Power Dissipation
1070 mW
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
4.2.1
RESET SOURCE
Digital Reset
Virtual PHY
Port 2 PHY
Port 1 PHY
Soft Reset
nRST Pin
Note 4.1
Chip-Level Resets
A chip-level reset event activates all internal resets, effectively resetting the entire LAN9311/LAN9311i.
Configuration straps are latched, and the EEPROM Loader is run as a result of chip-level resets. A
chip-level reset is initiated by assertion of any of the following input events:
Chip-level reset completion/configuration can be determined by polling the READY bit of the
Configuration Register (HW_CFG)
When set, the READY bit indicates that the reset has completed and the device is ready to be
accessed.
With the exception of the
Register
(RESET_CTL), read access to any internal resources is forbidden while the READY bit is cleared.
Writes to any address are invalid until the READY bit is set.
Note: The LAN9311/LAN9311i must be read at least once after any chip-level reset to ensure that
POR
Power-On Reset (POR)
nRST Pin Reset
write operations function properly.
Table 4.1 Reset Sources and Affected LAN9311/LAN9311i Circuitry
(PMT_CTRL),
In the case of a soft reset, the EEPROM Loader is run, but loads only the MAC address
into the Host MAC. No other values are loaded by the EEPROM Loader in this case.
X
X
X
X
X
X
Byte Order Test Register
Hardware Configuration Register
X
X
X
or
DATASHEET
X
X
X
X
X
Power Management Control Register (PMT_CTRL)
37
X
X
X
X
X
X
X
X
(BYTE_TEST), and
(HW_CFG),
X
X
X
X
X
X
Power Management Control
Reset Control Register
X
X
X
Revision 1.7 (06-29-10)
X
X
until it is set.
Note 4.1
Hardware
X
X
X
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