SI5326C-C-GM Silicon Laboratories Inc, SI5326C-C-GM Datasheet - Page 17
SI5326C-C-GM
Manufacturer Part Number
SI5326C-C-GM
Description
DSPLL 36-Pin QFN EP
Manufacturer
Silicon Laboratories Inc
Type
Jitter Attenuatorr
Datasheet
1.SI5326B-C-GM.pdf
(72 pages)
Specifications of SI5326C-C-GM
Package
36QFN EP
Operating Temperature
-40 to 85 °C
Pll
Yes
Input
Clock
Output
CML, CMOS, LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
2:2
Differential - Input:output
Yes/Yes
Frequency - Max
346MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
1.71 V ~ 3.63 V
Mounting Type
Surface Mount
Package / Case
36-QFN
Frequency-max
346MHz
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
QFN EP
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
336-1746
336-1746-5
336-1746
336-1746-5
336-1746
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI5326C-C-GM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
3. Typical Application Circuit
Note: For an example schematic and layout, refer to the Si5325/26-EVB User’s Guide.
Note: For an example schematic and layout, refer to the Si5325/26-EVB User’s Guide.
Option 1:
Option 2:
Input
Clock
Sources*
Option 1:
Option 2:
Figure 5. Si5326 Typical Application Circuit (SPI Control Mode)
Figure 4. Si5326 Typical Application Circuit (I
Control Mode (L)
Crystal/Ref Clk Rate
Input
Clock
Sources*
Control Mode (H)
Crystal/Ref Clk Rate
Crystal
Reset
Refclk+
Refclk–
Crystal
130
130
82
82
Reset
Refclk+
Refclk–
130
130
82
82
V
V
DD
DD
= 3.3 V
= 3.3 V
V
V
DD
DD
= 3.3 V
= 3.3 V
V
DD
15 k
15 k
130
130
82
82
V
0.1 µF
0.1 µF
Notes:
DD
15 k
15 k
130
130
82
82
0.1 µF
0.1 µF
Notes:
System
Supply
Power
1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).
3. I
CKIN2+
CKIN2–
CMODE
RST
CKIN1+
CKIN1–
XA
XB
RATE[1:0]
XA
XB
System
Supply
Power
2
1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).
C-required pull-up resistors not shown.
CKIN2+
CKIN2–
CMODE
RST
CKIN1+
CKIN1–
XA
XB
RATE[1:0]
XA
XB
2
Ferrite
Bead
2
Ferrite
Bead
Si5326
Si5326
Rev. 1.0
C
C
C
C
4
1
2
3
C
C
C
C
1 µF
0.1 µF
0.1 µF
0.1 µF
1
2
3
4
1 µF
0.1 µF
0.1 µF
0.1 µF
CKOUT1+
CKOUT1–
CKOUT2+
CKOUT2–
INT_C1B
CS_CA
CKOUT1+
CKOUT1–
CKOUT2+
CKOUT2–
A[2:0]
SDA
INT_C1B
DEC
SCL
C2B
LOL
CS_CA
INC
SCLK
SDO
DEC
C2B
LOL
SDI
INC
SS
0.1 µF
0.1 µF
0.1 µF
0.1 µF
2
0.1 µF
0.1 µF
0.1 µF
0.1 µF
100
100
Output Phase Control
C Control Mode)
Output Phase Control
100
100
Interrupt/CKIN1 Invalid Indicator
CKIN2 Invalid Indicator
PLL Loss of Lock Indicator
Serial Port Address
Serial Data
Serial Clock
Clock Select/Clock Active
Interrupt/CLKIN1 Invalid Indicator
CLKIN2 Invalid Indicator
PLL Loss of Lock Indicator
Slave Select
Serial Data Out
Serial Data In
Serial Clock
Clock Select/Clock Active
+
–
+
–
+
+
–
–
I2C Interface
Clock Outputs
SPI Interface
Clock Outputs
Si5326
17