SI5326C-C-GM Silicon Laboratories Inc, SI5326C-C-GM Datasheet - Page 30

• Manufacturer Part Number: SI5326C-C-GM
• Description: DSPLL 36-Pin QFN EP
• Manufacturer: Silicon Laboratories Inc
• Type: Jitter Attenuatorr

Specifications of SI5326C-C-GM

• Package: 36QFN EP
• Operating Temperature: -40 to 85 °C
• Pll: Yes
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 346MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 1.71 V ~ 3.63 V
• Mounting Type: Surface Mount
• Package / Case: 36-QFN
• Frequency-max: 346MHz
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: QFN EP
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1746; 336-1746-5; 336-1746

Si5326
Reset value = 0100 0000
Reset value = 0000 0000
30
Register 11.
Register 16.
Name
Name
Type
Type
7:2
7:0
Bit
Bit
Bit
Bit
1
0
CLAT [7:0]
Reserved
PD_CK2
PD_CK1
Name
Name
D7
D7
Reserved.
PD_CK2.
This bit controls the powerdown of the CKIN2 input buffer.
0: CKIN2 enabled
1: CKIN2 disabled
PD_CK1.
This bit controls the powerdown of the CKIN1 input buffer.
0: CKIN1 enabled
1: CKIN1 disabled
CLAT [7:0].
With INCDEC_PIN = 0, this register sets the phase delay for CKOUTn in units of
1/Fosc. This can take as long as 20 seconds.
01111111 = 127/Fosc (2s compliment)
00000000 = 0
10000000 = -128/Fosc (2s compliment)
If NI_HS[2:0] = 000, increasing CLAT does not work.
D6
D6
D5
D5
Reserved
R
Rev. 1.0
D4
D4
CLAT [7:0]
R/W
Function
Function
D3
D3
D2
D2
PD_CK2
R/W
D1
D1
PD_CK1
R/W
D0
D0