SI5326C-C-GM Silicon Laboratories Inc, SI5326C-C-GM Datasheet - Page 29

DSPLL 36-Pin QFN EP

SI5326C-C-GM

Manufacturer Part Number
SI5326C-C-GM
Description
DSPLL 36-Pin QFN EP
Manufacturer
Silicon Laboratories Inc
Type
Jitter Attenuatorr
Datasheet

Specifications of SI5326C-C-GM

Package
36QFN EP
Operating Temperature
-40 to 85 °C
Pll
Yes
Input
Clock
Output
CML, CMOS, LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
2:2
Differential - Input:output
Yes/Yes
Frequency - Max
346MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
1.71 V ~ 3.63 V
Mounting Type
Surface Mount
Package / Case
36-QFN
Frequency-max
346MHz
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
QFN EP
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
336-1746
336-1746-5
336-1746

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI5326C-C-GM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Company:
Part Number:
SI5326C-C-GMR
Quantity:
1 507
Reset value = 0000 0000
Register 10.
Name
Type
7:4
1:0
Bit
Bit
3
2
DSBL2_REG DSBL2_REG.
DSBL1_REG DSBL1_REG.
Reserved
Reserved
Name
D7
Reserved.
This bit controls the powerdown of the CKOUT2 output buffer. If disable mode is
selected, the N2_LS output divider is also powered down.
0: CKOUT2 enabled
1: CKOUT2 disabled
This bit controls the powerdown of the CKOUT1 output buffer. If disable mode is
selected, the N1_LS output divider is also powered down.
0: CKOUT1 enabled
1: CKOUT1 disabled
Reserved.
D6
Reserved
R
D5
Rev. 1.0
D4
DSBL2_
Function
REG
R/W
D3
DSBL1_
REG
R/W
D2
Reserved
D1
R
Si5326
Reserved
D0
R
29

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