SI5326C-C-GM Silicon Laboratories Inc, SI5326C-C-GM Datasheet - Page 70

• Manufacturer Part Number: SI5326C-C-GM
• Description: DSPLL 36-Pin QFN EP
• Manufacturer: Silicon Laboratories Inc
• Type: Jitter Attenuatorr

Specifications of SI5326C-C-GM

• Package: 36QFN EP
• Operating Temperature: -40 to 85 °C
• Pll: Yes
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 346MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 1.71 V ~ 3.63 V
• Mounting Type: Surface Mount
• Package / Case: 36-QFN
• Frequency-max: 346MHz
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: QFN EP
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1746; 336-1746-5; 336-1746

Si5326
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70
OCUMENT
Updated LVTTL to LVCMOS is Table 2, “Absolute
Maximum Ratings,” on page 6.
Added Figure 3, “Typical Phase Noise Plot,” on page
16.
Updated Figure 4, “Si5326 Typical Application
Circuit (I
Typical Application Circuit (SPI Control Mode),” on
page 17 to show preferred external reference
interface.
Updated “5.Register Map”.
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Updated "8. Ordering Guide" on page 65.
Added "9. Package Outline: 36-Pin QFN" on page
66.
Added “10.Recommended PCB Layout”.
Changed 1.8 V operating range to ±5%.
Updated Table 1 on page 4.
Updated Table 2 on page 6.
Updated Table 11 on page 66.
Added table under Figure 3 on page 16.
Updated "4. Functional Description" on page 18.
Clarified "5. Register Map" on page 20 including pull-
up/pull-down.
Updated Table 1 on page 4.
Added "11. Si5326 Device Top Mark" on page 69.
Changed “latency” to “skew” throughout.
Updated Table 1 on page 4.
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Updated Figure 4 on page 17.
Updated Figure 5, “Si5326 Typical Application
Circuit (SPI Control Mode),” on page 17.
Updated "5. Register Map" on page 20.
Updated "9. Package Outline: 36-Pin QFN" on page
66.
Added Figure 9, “Ground Pad Recommended
Layout,” on page 67
Added Register Map
Added RATE0 and changed RATE to RATE1 and
expanded RATE[1:0] description.
Changed font of register names to underlined italics.
Updated Thermal Resistance Junction to Ambient
typical specification.
2
C Control Mode),” and Figure 5, “Si5326
C
HANGE
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IST
Rev. 1.0
Revision 0.41 to Revision 0.42
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Revision 0.44 to Revision 1.0
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Text added to section "5. Register Map" on page 20.
Replaced Figure 9.
Updated Rise/Fall time values.
Changed register address labels to decimal.
Updated first page format to add chip image and pin
out
Updated Functional Block Diagram
Updated Section “1.Electrical Specifications” to
include ac/dc specifications from the Si53xx Family
Reference Manual (FRM)
Updated typical phase noise performance in Section
“2.Typical Phase Noise Performance”
Added INC/DEC pins to Figure 4 and Figure 5
Clarified the format for FLAT [14:0]
Added list of weak pull up/down resistors in Table 10,
“Si5326 Pull up/Pull down,” on page 64
Updated register maps 19, 20, 46, 47, 55, 142, 143,
185
Added note to typical application circuits in Section
“3.Typical Application Circuit”
Added evaluation board part number to “8.Ordering
Guide”
Updated Section “11.Si5326 Device Top Mark”
Updated Table 5, “Jitter Generation,” on page 14;
filled in all TBDs, and lowered typical RMS values