MT46H16M16LFBF-6:H Micron Technology Inc, MT46H16M16LFBF-6:H Datasheet
MT46H16M16LFBF-6:H
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MT46H16M16LFBF-6:H Summary of contents
Page 1
... Partial-array self refresh (PASR) • Deep power-down (DPD) • Status read register (SRR) • Selectable output drive strength (DS) • Clock stop capability • 64ms refresh PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Options • DDQ – 1.8V/1.8V • Configuration – ...
Page 2
... LG = Reduced page-size addressing FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM 16M16 ...
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... Rev. G, Production – 09/09 .......................................................................................................................... 94 Rev. F, Production – 4/09 ............................................................................................................................ 94 Rev. E, Production – 3/09 ............................................................................................................................ 94 PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. ...
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... Update – 05/08 ........................................................................................................................................... 95 Update – 03/08 ........................................................................................................................................... 95 Update – 12/07 ........................................................................................................................................... 95 Update – 07/07 ........................................................................................................................................... 96 PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. ...
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... Table 16: Truth Table – Current State Bank n – Command to Bank m .............................................................. 41 Table 17: Truth Table – CKE .......................................................................................................................... 44 Table 18: Burst Definition Table .................................................................................................................... 50 PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. ...
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... Figure 46: Bank Write – With Auto Precharge .................................................................................................. 85 Figure 47: Bank Write – Without Auto Precharge ............................................................................................. 86 Figure 48: Auto Refresh Mode ........................................................................................................................ 87 Figure 49: Self Refresh Mode ......................................................................................................................... 89 Figure 50: Power-Down Entry (in Active or Precharge Mode) .......................................................................... 90 PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM t t DQSQ, QH, and Data Valid Window (x16) ................................................... DQSQ, QH, and Data Valid Window (x32) ...
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... Figure 51: Power-Down Mode (Active or Precharge) ....................................................................................... 91 Figure 52: Deep Power-Down Mode .............................................................................................................. 92 Figure 53: Clock Stop Mode ........................................................................................................................... 93 PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. ...
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... General Description The 256Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access mem- ory containing 268,435,456 bits internally configured as a quad-bank DRAM. Each of the x16’s 67,108,864-bit banks is organized as 8192 rows by 512 columns by 16 bits. Each of the x32’s 67,108,864-bit banks is organized as 4096 rows by 512 columns by 32 bits. In the reduced page-size (LG) option, each of the x32’ ...
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... WE# CAS# Refresh RAS# counter Standard mode register Extended mode register Address address BA0, BA1 register PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Bank 2 Bank 1 Bank 0 Row- address row- Bank 0 address Mux memory latch array and decoder Sense amplifiers ...
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... Control CS# logic WE# CAS# RAS# Standard mode register Extended mode register Address, Address BA0, BA1 register PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Bank 2 Bank 1 Refresh counter Bank 0 Row- row- address Bank 0 address MUX memory latch array and ...
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... Ball Assignments and Descriptions Figure 4: 60-Ball VFBGA – 8mm x 9mm (Top View test pin that must be tied to V Note: PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM DQ15 V SS SSQ V DQ13 DQ14 DDQ V DQ11 DQ12 SSQ V DQ9 DQ10 ...
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... Figure 5: 90-Ball VFBGA – 8mm x 13mm (Top View test pin that must be tied to V Note: PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM DQ31 V SS SSQ V DQ29 DQ30 DDQ V DQ27 DQ28 SSQ V DQ25 DQ26 DDQ V DQS3 DQ24 SSQ ...
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... V Supply SS PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Ball Assignments and Descriptions Description Clock the system clock input. CK and CK# are differential clock inputs. All ad- dress and control input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Input and output data is referenced to the cross- ing of CK and CK# (both directions of the crossing) ...
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... Input TEST Input 1. Balls marked RFU may or may not be connected internally. These balls should not be Note: PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Description No connect: May be left unconnected. Reserved for future use. Test pin: Must be tied used. Contact factory for details. ...
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... Solder ball material: SAC105 (98.5% Sn, 1% Ag, 0.5% Cu). Dimensions apply solder balls post-reflow on Ø0.4 SMD ball pads. 7.2 CTR 0.8 TYP 1. All dimensions are in millimeters. Note: PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM 0.65 ±0.05 Ball ±0 ...
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... Solder ball material: SAC105 (98.5% Sn, 1%Ag, 0.5% Cu). Dimensions apply to solder balls post reflow on Ø0.4 SMD ball pads. 11.2 CTR 0.8 TYP 1. All dimensions are in millimeters. Note: PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM 0.65 ±0.05 Ball ±0.1 ...
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... DC output high voltage: Logic output low voltage: Logic Leakage current Input leakage current Any input 0V ≤ V ≤ (All other pins not under test = 0V) PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Symbol DDQ STG and V must be within 300mV of each other at all times. V ...
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... CK and CK# input slew rate must be ≥1 V/ns (2 V/ns if measured differentially). 11. V 12. The value of V 13. DQ and DM input slew rates must not deviate from DQS by more than 10%. 50ps must PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM /V = 1.70–1.95V DD DDQ Symbol ...
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... The input capacitance per pin group will not differ by more than this maximum amount 3. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maxi- PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Symbol C CK ...
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... Data bus inputs are stable Deep power-down current: Address and control balls are stable; Data bus inputs are stable PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – I Parameters 1.70–1.95V ...
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... Data bus inputs are stable Deep power-down current: Address and control pins are stable; Data bus inputs are stable PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – 1.70–1.95V DD DDQ ...
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... This limit is a nominal value and does not result in a fail. CKE is HIGH during REFRESH 12. Values for I 13. Typical values at 25˚C, not a maximum value. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – I Full array, 85˚C Full array, 45˚C 1/2 array, 85˚C 1/2 array, 45˚ ...
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... PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – I 0°C 10°C 20°C 30°C 40°C Temperature 23 DD 50°C 60°C 70°C 80°C 90°C Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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... DQS falling edge to CK ris- DSS ing – setup time Data valid output window DVW PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – AC Operating Conditions /V = 1.70–1.95V DD DDQ -5 -54 Min Max ...
Page 25
... Average periodic refresh in- REFI terval t AUTO REFRESH command RFC period t PRECHARGE command peri DQS read RPRE preamble PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – AC Operating Conditions /V = 1.70–1.95V DD DDQ -5 -54 Min Max Min Max t – CH, ...
Page 26
... The circuit shown below represents the timing reference load used in defining the rele- 5. The CK/CK# input reference voltage level (for timing referenced to CK/CK#) is the point PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – AC Operating Conditions /V = 1.70–1.95V ...
Page 27
... This is not a device limit. The device will operate with a negative value, but system per- 25 recommended that DQS be valid (HIGH or LOW before the WRITE command. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – AC Operating Conditions all parameters. theclock at which the READ command was registered; for the first data element ...
Page 28
... At least 1 clock cycle is required during 28. Clock must be toggled a minimum of two times during the PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – AC Operating Conditions a greater value for this parameter, but system performance (bus turnaround) will de- grade accordingly. ...
Page 29
... Based on nominal impedance of 25Ω (full strength Notes: 2. The full variation in driver current from minimum to maximum, due to process, voltage, PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Pull-Down Current (mA) Min Max 0.00 0.00 2.80 18.53 5 ...
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... Based on nominal impedance of 37Ω (three-quarter drive strength Notes: 2. The full variation in driver current from minimum to maximum, due to process, voltage, PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Pull-Down Current (mA) Min Max 0.00 0.00 1.96 12.97 3 ...
Page 31
... Based on nominal impedance of 55Ω (one-half drive strength Notes: 2. The full variation in driver current from minimum to maximum, due to process, voltage, 3. The I-V curve for one-quarter drive strength is approximately 50% of one-half drive PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Pull-Down Current (mA) Min Max 0.00 0.00 1 ...
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... Functional Description The Mobile LPDDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O. Single read or write access for the device consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock- cycle data transfers at the I/O ...
Page 33
... This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 8. Internal refresh counter controls row addressing; in self refresh mode all inputs and I/Os 9. BA0–BA1 select the standard mode register, extended mode register, or status register. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM CS ...
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... A[0:n] selects the row. This row remains active for accesses until a PRE- CHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Valid ...
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... READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM CK# CK CKE HIGH CS# ...
Page 36
... If a WRITE or a READ is in progress, the entire data burst must be complete prior to stopping the clock (see Clock Change Frequency (page 93)). A burst completion for WRITEs is defined when the write postamble and PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM CK# CK CKE HIGH ...
Page 37
... BA0 and BA1 select the bank. Otherwise, BA0 and BA1 are treated as “Don’t Care.” After a bank has been precharged the idle state and must be activa- ted prior to any READ or WRITE commands being issued to that bank. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM CK# CK CKE HIGH ...
Page 38
... AUTO REFRESH AUTO REFRESH is used during normal operation of the device and is analogous to CAS#- BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAM. The AUTO REFRESH command is nonpersistent and must be issued each time a refresh is required. Addressing is generated by the internal refresh controller. This makes the address bits a “ ...
Page 39
... BURST TERMINATE command with CKE LOW. Figure 13: DEEP POWER-DOWN Command RAS# CAS# Address BA0, BA1 PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM CK# CK CKE CS# WE# Don’t Care 39 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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... This table is bank-specific, except where noted (for example, the current state is for a 3. Current state definitions: 4. The states listed below must not be interrupted by a command issued to the same bank. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM CAS# WE# Command/Action X X ...
Page 41
... L L PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Read with auto-precharge enabled: Starts with registration of a READ command with auto precharge enabled and ends when be in the idle state. Write with auto-precharge enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when will be in the idle state ...
Page 42
... This table applies when CKE Notes: 2. This table describes alternate bank operation, except where noted (for example, the cur- 3. Current state definitions: PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM CAS# WE# Command/Action H H ACTIVE (select and activate row) ...
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... All states and sequences not shown are illegal or reserved. 6. Requires appropriate DM masking WRITE command can be applied after the completion of the READ burst; otherwise, a PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM From Command To Command READ with READ or READ with auto precharge ...
Page 44
... CKE Notes: 2. Current state is the state of the DDR SDRAM immediately prior to clock edge n. 3. COMMAND 4. All states and sequences not shown are illegal or reserved. 5. DESELECT or NOP commands should be issued on each clock edge occurring during the 6. After exiting deep power-down mode, a full DRAM initialization sequence is required. ...
Page 45
... WRITE A PRE ACT = ACTIVE AREF = AUTO REFRESH BST = BURST TERMINATE CKEH = Exit power-down CKEL = Enter power-down DPD = Enter deep power-down PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Self refresh DPDX Deep SREFX power- down SREF DPD SRR ...
Page 46
... Issue NOP or DESELECT commands for at least After steps 1–10 are completed, the device has been properly initialized and is ready to receive any valid command. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM ) and I/O power ( recommended that V and V DD must never exceed V ...
Page 47
... PRE = PRECHARGE command; LMR = LOAD MODE REGISTER command AUTO RE- 2. NOP or DESELECT commands are required for at least 200μs. 3. Other valid commands are possible. 4. NOPs or DESELECTs are required during this time. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM T1 Ta0 ...
Page 48
... CK stable DD 1. PRE = PRECHARGE command; LMR = LOAD MODE REGISTER command AUTO RE- Notes: 2. NOP or DESELECT commands are required for at least 200μs. 3. Other valid commands are possible. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM T1 T0 Ta0 ( ( ( ( ...
Page 49
... The integer n is equal to the most significant address bit. Note: Burst Length Read and write accesses to the device are burst-oriented, and the burst length (BL) is programmable. The burst length determines the maximum number of column loca- PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM BA1 BA0 An ... A10 ...
Page 50
... The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address. Table 18: Burst Definition Table Burst Length Starting Column Address PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Order of Accesses Within a Burst Type = Sequential A0 0 0 0-1-2 1-2-3 2-3-0 3-0-1-2 A1 ...
Page 51
... For the READ command is registered at clock edge n, then the data will be nominally available clocks + tered at clock edge n, then the data will be nominally available clock + PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Order of Accesses Within a Burst Type = Sequential 0 0 ...
Page 52
... A[n:7] each set to zero, and bits A[6:0] set to the desired values. All other combinations of values for A[n:7] are reserved for future use. Reserved states should not be used because unknown operation or incompatibility with future versions may result. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM T0 T1 T1n CK# CK ...
Page 53
... Programming the temperature-compensated self refresh (TCSR) bits will have no effect on the device. The self refresh oscillator will continue to refresh at the optimal factory-programmed rate for the device temperature. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM BA0 An ... A10 ...
Page 54
... The output driver settings are 25Ω, 37Ω, and 55Ω internal impedance for full, three-quarter, and one-half drive strengths, respectively. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM Extended Mode Register 54 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 55
... Burst length is fixed to 2 for SRR regardless of the value programmed by the mode register. 5. The second bit of the data-out burst is a “Don’t Care.” PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM set SRR; only NOP or DESELECT commands are supported during the mand is issued ...
Page 56
... Reserved Notes: 1. Reserved bits should be set to 0 for future compatibility. 2. Refresh multiplier is based on the memory device on-board temperature sensor. Re- PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 S12 S11 S10 ...
Page 57
... The mini- mum time interval between successive ACTIVE commands to different banks is defined t by RRD. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM t RCD specification. 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. Bank/Row Activation t RC. © ...
Page 58
... READ command, where x equals the number of desired data element pairs. This is shown in Figure 28 (page 65). Following the PRECHARGE command, a subsequent PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM t DQSQ (valid data-out skew), t DQSCK (DQS transition skew to CK) and 58 Micron Technology, Inc ...
Page 59
... READ Address Bank a, Col n DQS DQ T0 CK# CK Command READ Address Bank a, Col n DQS Notes Shown with nominal PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n NOP NOP OUT OUT T1 T2 T2n NOP NOP data-out from column n. ...
Page 60
... DQS Notes (if 4, the bursts are concatenated 16, the second burst interrupts 3. Shown with nominal 4. Example applies only when READ commands are issued to same device. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n NOP READ Bank, Col b ...
Page 61
... Col n DQS Notes (if burst 16, the second burst interrupts the first). 3. Shown with nominal 4. Example applies when READ commands are issued to different devices or nonconsecu- PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n T3 NOP NOP READ Bank, Col b ...
Page 62
... READ Bank, Address Col n DQS Notes ( 16, the following burst interrupts the previous). 3. READs are to an active row in any bank. 4. Shown with nominal PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n READ READ Bank, Bank, Col x Col ...
Page 63
... CK# CK Command 1 READ Bank a, Address Col n DQS 16. Notes: 2. BST = BURST TERMINATE command; page remains open Shown with nominal 5. CKE = HIGH. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n 2 BST NOP OUT OUT T1 T2 T2n 2 BST NOP ...
Page 64
... the cases shown (applies for bursts of 8 and 16 as well the BST com- Notes: 2. BST = BURST TERMINATE command; page remains open Shown with nominal 6. CKE = HIGH. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n 2 BST NOP ...
Page 65
... Notes: 2. PRE = PRECHARGE command. 3. ACT = ACTIVE command Shown with nominal 6. READ-to-PRECHARGE equals 2 clocks, which enables 2 data pairs of data-out READ command with auto precharge enabled, provided PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n 2 NOP PRE Bank a, ...
Page 66
... DQ (First data no longer valid) DQ[15:8] and UDQS, collectively 1. Notes transitioning after DQS transitions define the 4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7. 5. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM t t DQSQ, QH, and Data Valid Window (x16 T2n 1 1 ...
Page 67
... The data valid window is derived for each DQS transition and is 7. DQ[7:0] and DQS0 for byte 0; DQ[15:8] and DQS1 for byte 1; DQ[23:16] and DQS2 for PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM t t DQSQ, QH, and Data Valid Window (x32) ...
Page 68
... NOP DQS or LDQS/UDQS 2 All DQ values, collectively 3 1. Commands other than NOP can be valid during this cycle. Notes transitioning after DQS transitions define 3. All DQ must transition by 4. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM and DQSCK T2n NOP ...
Page 69
... Data for any WRITE burst can be followed by a subsequent PRECHARGE command. To follow a WRITE without truncating the WRITE burst, Figure 41 (page 78). PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM DQSS [MAX]) might not be obvious, they have also been included. Figure 34 69 Micron Technology, Inc ...
Page 70
... For x16, LDQS controls the lower byte; UDQS controls the upper byte. For x32, DQS0 con- 5. For x16, LDM controls the lower byte; UDM controls the upper byte. For x32, DM0 con- PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM t WR period are written to the internal array, and 1 ...
Page 71
... NOP commands are shown for ease of illustration; other commands may be valid at Notes the case shown. 3. PRE = PRECHARGE. 4. Disable auto precharge. 5. Bank “Don’t Care” if A10 is HIGH at T8 PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM NOP NOP ...
Page 72
... Address t DQSS (NOM) t DQSS (MIN) t DQSS (MAX uninterrupted burst shown. Notes: 2. A10 is LOW with the WRITE command (auto precharge is disabled PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM T0 T1 CK# CK 1,2 WRITE NOP Bank a, Col b t DQSS DQS 3 ...
Page 73
... Command 1,2 WRITE Bank, Address Col b t DQSS (NOM) DQS Each WRITE command can be to any bank. Notes uninterrupted burst shown PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n 1, 2 NOP WRITE Bank, Col (n) = data-in for column b (n). ...
Page 74
... Col b t DQSS (NOM) DQS DQ 3,4 DM Notes: 1. Each WRITE command can be to any bank. 2. Programmed cases shown ( the next data-in following D PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n 1,2 1,2 WRITE WRITE Bank, Bank, Col x Col n D ...
Page 75
... The READ and WRITE commands are to the same device. However, the READ and WRITE Notes: 2. A10 is LOW with the WRITE command (auto precharge is disabled uninterrupted burst shown PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n T3 NOP NOP ...
Page 76
... An interrupted burst shown; 2 data elements are written. Notes: 2. A10 is LOW with the WRITE command (auto precharge is disabled DQS is required at T2 and T2n (nominal case) to register DM PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n T3 NOP NOP ...
Page 77
... An interrupted burst shown; 1 data element is written, 3 are masked. Notes: 2. A10 is LOW with the WRITE command (auto precharge is disabled DQS is required at T2 and T2n (nominal case) to register DM PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n T3 NOP NOP ...
Page 78
... An uninterrupted burst shown. 2. A10 is LOW with the WRITE command (auto precharge is disabled). 3. PRE = PRECHARGE. 4. The PRECHARGE and WRITE commands are to the same device. However, the PRE PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n T3 NOP NOP ...
Page 79
... An interrupted burst shown; two data elements are written. Notes: 2. A10 is LOW with the WRITE command (auto precharge is disabled). 3. PRE = PRECHARGE DQS is required at T4 and T4n to register DM PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n T3 NOP NOP NOP ...
Page 80
... A10 is LOW with the WRITE command (auto precharge is disabled). 3. PRE = PRECHARGE DQS is required at T4 and T4n to register DM burst used, DQS and DM are not required at T3, T3n, T4, and T4n PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n T3 NOP NOP ...
Page 81
... Figure 45 (page 84). Bank WRITE operations with and without auto precharge are shown in Figure 46 (page 85) and Figure 47 (page 86). PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM t RP) after the PRECHARGE command is issued. Input A10 deter (the precharge period) begins. For READ with auto pre- ...
Page 82
... In either situation, all other related limitations apply (for example, contention between READ data and WRITE data must be avoided). PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM 82 Micron Technology, Inc. reserves the right to change products or specifications without notice. Auto Precharge ...
Page 83
... DQ 1. NOP commands are shown for ease of illustration; other commands may be valid at Notes the case shown. 3. Enable auto precharge. 4. Refer to Figure 29 (page 66) and Figure 30 (page 67) for detailed DQS and DQ timing PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM ...
Page 84
... NOP commands are shown for ease of illustration; other commands may be valid at Notes the case shown. 3. PRE = PRECHARGE. 4. Disable auto precharge. 5. Bank “Don’t Care” if A10 is HIGH at T5. 6. The PRECHARGE command can only be applied PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM ...
Page 85
... IS IH BA0, BA1 Bank x DQS NOP commands are shown for ease of illustration; other commands may be valid at Notes the case shown. 3. Enable auto precharge PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM n = data out from column n. OUT NOP WRITE ...
Page 86
... DQ DM Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid the case shown. 3. PRE = PRECHARGE. 4. Disable auto precharge. 5. Bank “Don’t Care” if A10 is HIGH at T8 PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM NOP ...
Page 87
... AUTO REFRESH Operation Auto refresh mode is used during normal operation of the device and is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAM. The AUTO REFRESH com- mand is nonpersistent and must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a “ ...
Page 88
... SELF REFRESH command must not be used as a substitute for the AUTO REFRESH command. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM t XSR to complete any internal refresh already in progress. 88 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 89
... Care.” The power-down state is synchronously exited when CKE is registered HIGH (in conjunction with a NOP or DESELECT command). NOP or DESELECT commands must be maintained on the command bus until satisfied. See Figure 51 (page 91) for a detailed illustration of power-down mode. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM T1 Ta0 ( ( ) ...
Page 90
... Figure 50: Power-Down Entry (in Active or Precharge Mode) RAS#, CAS#, WE# RAS#, CAS#, WE# PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM CK# CK CKE CS# Or CS# Address BA0, BA1 Don’t Care 90 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 91
... LOW to maintain DPD mode. The clock must be stable prior to exiting DPD mode. To exit DPD mode, assert CKE HIGH with either a NOP or DESELECT com- mand present on the command bus. After exiting DPD mode, a full DRAM initialization sequence is required. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n ...
Page 92
... All banks idle with no activity on the data bus 1. Clock must be stable prior to CKE going HIGH. Notes: 2. DPD = deep power-down. 3. Upon exit of deep power-down mode, a full DRAM initialization sequence is required. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM 1 T1 ...
Page 93
... The device enables the clock to change frequency during operation only if all timing parameters are met and all refresh requirements are satisfied. The clock can be stopped altogether if there are no DRAM operations in progress that would be affected by this change. Any DRAM operation already in process must be com- pleted before entering clock stop mode ...
Page 94
... Table 9, Electrical Characteristics and Recommended AC Operating Conditions: Changed values for and Rev. A, Advance – 08/08 • Initial release. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM t CKE symbol. Specifications and Conditions (x16): Tightened x16 and I values for all speed grades. ...
Page 95
... Concurrent Auto Precharge: Updated figure references. Update – 12/07 • Figure 19, Extended Mode Register: Updated to include mid-strength driver informa- tion. PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM t RAS lock-out. 95 Micron Technology, Inc. reserves the right to change products or specifications without notice. Revision History ...
Page 96
... Figure 21, Status Register Definition: Corrected headings for density. Update – 07/07 • Initial Release PDF: 09005aef834bf85b 256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN 256Mb: x16, x32 Mobile LPDDR SDRAM 96 Micron Technology, Inc. reserves the right to change products or specifications without notice. Revision History ©2008 Micron Technology, Inc. All rights reserved. ...