MT46H16M16LFBF-6:H Micron Technology Inc, MT46H16M16LFBF-6:H Datasheet - Page 69

• Manufacturer Part Number: MT46H16M16LFBF-6:H
• Description: DRAM Chip DDR SDRAM 256M-Bit 16Mx16 1.8V 60-Pin VFBGA Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr
• Series: -r

Specifications of MT46H16M16LFBF-6:H

• Package: 60VFBGA
• Density: 256 Mb
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 1.8 V
• Maximum Clock Rate: 166 MHz
• Maximum Random Access Time: 6.5|5 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Package / Case: 60-VFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

WRITE Operation
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN
WRITE bursts are initiated with a WRITE command, as shown in Figure 11 (page 37).
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is ena-
bled, the row being accessed is precharged at the completion of the burst. For the
WRITE commands used in the following illustrations, auto precharge is disabled. Basic
data input timing is shown in Figure 32 (page 70) (this timing applies to all WRITE
operations).
Input data appearing on the data bus is written to the memory array subject to the state
of data mask (DM) inputs coincident with the data. If DM is registered LOW, the corre-
sponding data will be written; if DM is registered HIGH, the corresponding data will be
ignored, and the write will not be executed to that byte/column location. DM operation
is illustrated in Figure 33 (page 71).
During WRITE bursts, the first valid data-in element will be registered on the first rising
edge of DQS following the WRITE command, and subsequent data elements will be reg-
istered on successive edges of DQS. The LOW state of DQS between the WRITE com-
mand and the first rising edge is known as the write preamble; the LOW state of DQS
following the last data-in element is known as the write postamble. The WRITE burst is
complete when the write postamble and
The time between the WRITE command and the first corresponding rising edge of DQS
(
WRITE diagrams show the nominal case. Where the two extreme cases (that is,
[MIN] and
(page 72) shows the nominal case and the extremes of
completion of a burst, assuming no other commands have been initiated, the DQ will
remain High-Z and any additional input data will be ignored.
Data for any WRITE burst can be concatenated with or truncated by a subsequent
WRITE command. In either case, a continuous flow of input data can be maintained.
The new WRITE command can be issued on any positive edge of clock following the
previous WRITE command. The first data element from the new burst is applied after
either the last element of a completed burst or the last desired data element of a longer
burst that is being truncated. The new WRITE command should be issued x cycles after
the first WRITE command, where x equals the number of desired data element pairs
(pairs are required by the 2n-prefetch architecture).
Figure 35 (page 73) shows concatenated bursts of 4. An example of nonconsecutive
WRITEs is shown in Figure 36 (page 73). Full-speed random write accesses within a
page or pages can be performed, as shown in Figure 37 (page 74).
Data for any WRITE burst can be followed by a subsequent READ command. To follow
a WRITE without truncating the WRITE burst,
ure 38 (page 75).
Data for any WRITE burst can be truncated by a subsequent READ command, as shown
in Figure 39 (page 76). Note that only the data-in pairs that are registered prior to the
t
masked with DM, as shown in Figure 40 (page 77).
Data for any WRITE burst can be followed by a subsequent PRECHARGE command. To
follow a WRITE without truncating the WRITE burst,
Figure 41 (page 78).
WTR period are written to the internal array, and any subsequent data-in should be
t
DQSS) is specified with a relatively wide range (75%–125% of one clock cycle). All
t
DQSS [MAX]) might not be obvious, they have also been included. Figure 34
69
256Mb: x16, x32 Mobile LPDDR SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
WR or
t
WTR should be met, as shown in Fig-
t
WTR are satisfied.
t
WR should be met, as shown in
t
DQSS for a burst of 4. Upon
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WRITE Operation
t
DQSS