MT48LC4M32LFF5-8 IT:G TR Micron Technology Inc, MT48LC4M32LFF5-8 IT:G TR Datasheet - Page 18

• Manufacturer Part Number: MT48LC4M32LFF5-8 IT:G TR
• Description: DRAM Chip Mobile SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA T/R
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48LC4M32LFF5-8 IT:G TR

• Density: 128 Mb
• Maximum Clock Rate: 125 MHz
• Package: 90VFBGA
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 19|8|7 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 90-VFBGA
• Organization: 4Mx32
• Address Bus: 14b
• Access Time (max): 19/8/7ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 115mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 7:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
M13 M12
0
1
0
0
Mode Register Definition
Program Extended Mode Register
M9
0
0
M11
Mode Register Definition
Program Mode Register
0
–
Programmed Burst Length
Single Location Access
M10
0
–
Write Burst Mode
Valid
M9
–
M8
0
–
M13
BA1
13
MR
M7
0
–
12
M12
BA0
M6–M0
Valid
Reserved
11
–
A11
M11
M6
0
0
0
0
1
1
1
1
10
A10
M10
M5
All other states reserved
0
0
1
1
0
0
1
1
WB
Normal Operation
M4
Operating Mode
A9
M9
9
0
1
0
1
0
1
0
1
18
Op Mode
A8
M8
8
CAS Latency
A7
M7
7
Reserved
Reserved
Reserved
Reserved
Reserved
CAS Latency BT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
2
3
A6
M6
6
5
A5
M5
128Mb: x16, x32 Mobile SDRAM
4
A4
M4
M3
A3
3
M2
Burst Length
0
0
0
0
1
1
1
1
M2
A2
2
M3
0
1
M1
0
0
1
1
0
0
1
1
M1
1
A1
M0
0
1
0
1
0
1
0
1
©2001 Micron Technology, Inc. All rights reserved.
Register Definition
A0
M0
0
Reserved
Reserved
Reserved
Reserved
M3 = 0
Interleaved
Burst Type
Sequential
Burst Length
1
2
4
8
Address Bus
Mode
Register (Mx)
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8