MT48LC4M32LFF5-8 IT:G TR Micron Technology Inc, MT48LC4M32LFF5-8 IT:G TR Datasheet - Page 58

• Manufacturer Part Number: MT48LC4M32LFF5-8 IT:G TR
• Description: DRAM Chip Mobile SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA T/R
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48LC4M32LFF5-8 IT:G TR

• Density: 128 Mb
• Maximum Clock Rate: 125 MHz
• Package: 90VFBGA
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 19|8|7 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 90-VFBGA
• Organization: 4Mx32
• Address Bus: 14b
• Access Time (max): 19/8/7ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 115mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
22. V
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
24. Auto precharge mode only. The precharge timing budget (
25. Manual precharge mode only.
26. JEDEC and PC100 specify 3 clocks.
27. Parameter guaranteed by design.
28. PC100 specifies a maximum of 4pF.
29. PC100 specifies a maximum of 5pF.
30. PC100 specifies a maximum of 6.5pF.
31. For -75M, CL = 3 and
32. CKE is HIGH during refresh command period
33. Specified with I/Os in steady state condition.
cannot be greater than one-third of the cycle rate. V
a pulse width ≤ 3ns and cannot be greater than one-third of the cycle rate.
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including
used to reduce the data rate.
after the first clock delay after the last WRITE is executed.
t
limit is actually a nominal value and does not result in a fail value.
CK = 10ns.
IH
overshoot: V
IH
(MAX) = V
t
CK = 7.5ns; for -8, CL = 3 and
58
DD
Q + 2V for a pulse width ≤ 3ns, and the pulse width
t
WR, and PRECHARGE commands). CKE may be
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x16, x32 Mobile SDRAM
t
RFC (MIN) else CKE is LOW. The I
IL
t
CK = 8ns; for -10, CL = 3 and
undershoot: V
t
RP) begins at 5.4ns for -8
©2001 Micron Technology, Inc. All rights reserved.
IL
(MIN) = –2V for
Notes
DD
6