MT48LC4M32LFF5-8 IT:G TR Micron Technology Inc, MT48LC4M32LFF5-8 IT:G TR Datasheet - Page 75

• Manufacturer Part Number: MT48LC4M32LFF5-8 IT:G TR
• Description: DRAM Chip Mobile SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA T/R
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48LC4M32LFF5-8 IT:G TR

• Density: 128 Mb
• Maximum Clock Rate: 125 MHz
• Package: 90VFBGA
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 19|8|7 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 90-VFBGA
• Organization: 4Mx32
• Address Bus: 14b
• Access Time (max): 19/8/7ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 115mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 54:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
DQMU, DQML
COMMAND
A0–A9, A11
BA0, BA1
A10
CLK
CKE
DQ
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
Alternating Bank Write Accesses
BANK 0
T0
ROW
ROW
t CKH
t CMH
t AH
t AH
t AH
t CK
Notes:
t RCD - BANK 0
t RAS - BANK 0
t
t
RC - BANK 0
RRD
T1
NOP
1. For this example, BL = 4.
2. x16: A9 and A11 = “Don’t Care.”
ENABLE AUTO PRECHARGE
x32: A8, A9, and A11 = “Don’t Care.”
See Table 17 on page 53.
t CMS
t CL
t DS
COLUMN m 2
BANK 0
WRITE
T2
D
IN
t CMH
t CH
t DH
m
t DS
D
IN
T3
NOP
m + 1
t DH
t DS
D
BANK 1
ACTIVE
IN
T4
ROW
ROW
m + 2
75
t DH
t RCD - BANK 1
t DS
D
IN
T5
NOP
m + 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t DH
t WR - BANK 0
ENABLE AUTO PRECHARGE
COLUMN b 2
t DS
128Mb: x16, x32 Mobile SDRAM
BANK 1
WRITE
T6
D
IN
t DH
b
t DS
D
NOP
IN
T7
b + 1
t DH
t
RP - BANK 0
©2001 Micron Technology, Inc. All rights reserved.
t DS
D
Timing Diagrams
IN
NOP
T8
b + 2
t DH
t DS
D
BANK 0
ACTIVE
IN
T9
ROW
ROW
b + 3
t
t
DON’T CARE
RCD - BANK 0
WR - BANK 1
t DH