MT48LC4M32LFF5-8 IT:G TR Micron Technology Inc, MT48LC4M32LFF5-8 IT:G TR Datasheet - Page 35

• Manufacturer Part Number: MT48LC4M32LFF5-8 IT:G TR
• Description: DRAM Chip Mobile SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA T/R
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48LC4M32LFF5-8 IT:G TR

• Density: 128 Mb
• Maximum Clock Rate: 125 MHz
• Package: 90VFBGA
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 19|8|7 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 90-VFBGA
• Organization: 4Mx32
• Address Bus: 14b
• Access Time (max): 19/8/7ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 115mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

WRITEs
Figure 20:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
WRITE Command
WRITE bursts are initiated with a WRITE command, as shown in Figure 20.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge either is enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the WRITE
commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length burst, assuming no other
commands have been initiated, the DQ will remain High-Z, and any additional input
data will be ignored (see Figure 21 on page 36). A full-page burst will continue until
terminated. (At the end of the page, it will wrap to column 0 and continue.)
x16: A0–A8
x32: A0–A7
Data for any WRITE burst may be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command. An example is shown in Figure 21 on page 36. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst. The 128Mb SDRAM uses a pipe-
lined architecture and, therefore, does not require the 2n rule associated with a prefetch
architecture. A WRITE command can be initiated on any clock cycle following a previous
WRITE command. Full-speed random write accesses within a page can be performed to
the same bank, as shown in Figure 22 on page 36, or each subsequent WRITE may be
performed to a different bank.
A9, A11
BA0,1
RAS#
CAS#
WE#
CLK
CKE
A10
CS#
HIGH
VALID ADDRESS
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ADDRESS
ADDRESS
COLUMN
BANK
35
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x16, x32 Mobile SDRAM
©2001 Micron Technology, Inc. All rights reserved.
READs