MT48LC8M16A2B4-75:G TR Micron Technology Inc, MT48LC8M16A2B4-75:G TR Datasheet - Page 39
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MT48LC8M16A2B4-75:G TR
Manufacturer Part Number
MT48LC8M16A2B4-75:G TR
Description
DRAM Chip SDRAM 128M-Bit 8Mx16 3.3V 54-Pin VFBGA T/R
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC8M16A2P-75G_TR.pdf
(74 pages)
Specifications of MT48LC8M16A2B4-75:G TR
Density
128 Mb
Maximum Clock Rate
133 MHz
Package
54VFBGA
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
6|5.4 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (8Mx16)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
54-VFBGA
Organization
8Mx16
Address Bus
14b
Access Time (max)
6/5.4ns
Operating Supply Voltage (typ)
3.3V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
150mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Figure 30:
Figure 31:
WRITE with Auto Precharge
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
Internal
States
Internal
States
READ With Auto Precharge Interrupted by a READ
READ With Auto Precharge Interrupted by a WRITE
Notes:
Notes:
COMMAND
COMMAND
ADDRESS
BANK m
ADDRESS
BANK m
BANK n
BANK n
DQM
CLK
CLK
DQ
DQ
1. DQM is LOW.
1. DQM is HIGH at T2 to prevent D
• Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
1
rupt a WRITE on bank n when registered, with the data-out appearing CL later. The
precharge to bank n will begin after
bank m is registered. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m (Figure 32 on page 40).
Active
Page
READ - AP
BANK n,
Page Active
BANK n
COL a
T0
NOP
T0
READ with Burst of 4
READ - AP
BANK n,
Page Active
Page Active
BANK n
COL a
T1
T1
NOP
CL = 3 (BANK n)
READ with Burst of 4
CL = 3 (BANK n)
T2
T2
NOP
NOP
39
BANK m,
READ - AP
T3
BANK m
T3
COL d
OUT
D
NOP
OUT
a
Interrupt Burst, Precharge
READ with Burst of 4
a + 1 from contending with D
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
WR is met, where
TRANSITIONING DATA
BANK m,
WRITE - AP
TRANSITIONING DATA
COL d
BANK m
T4
T4
CL = 3 (BANK m)
D
NOP
d
IN
Interrupt Burst, Precharge
D
WRITE with Burst of 4
OUT
a
t
RP - BANK n
T5
T5
d + 1
NOP
NOP
D
IN
D
a + 1
128Mb: x4, x8, x16 SDRAM
OUT
t
RP - BANK n
t
WR begins when the READ to
T6
T6
d + 2
NOP
NOP
D
IN
D
OUT
©1999 Micron Technology, Inc. All rights reserved.
d
IN
DON’T CARE
DON’T CARE
at T4.
Idle
T7
T7
t WR - BANK m
d + 3
NOP
NOP
D
t RP - BANK m
IN
Precharge
Write-Bac k
D
d + 1
OUT
Idle
Operations