MT48LC8M16A2B4-75:G TR Micron Technology Inc, MT48LC8M16A2B4-75:G TR Datasheet - Page 43
![DRAM Chip SDRAM 128M-Bit 8Mx16 3.3V 54-Pin VFBGA T/R](/photos/7/22/72286/557-54-fbga_sml.jpg)
MT48LC8M16A2B4-75:G TR
Manufacturer Part Number
MT48LC8M16A2B4-75:G TR
Description
DRAM Chip SDRAM 128M-Bit 8Mx16 3.3V 54-Pin VFBGA T/R
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC8M16A2P-75G_TR.pdf
(74 pages)
Specifications of MT48LC8M16A2B4-75:G TR
Density
128 Mb
Maximum Clock Rate
133 MHz
Package
54VFBGA
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
6|5.4 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (8Mx16)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
54-VFBGA
Organization
8Mx16
Address Bus
14b
Access Time (max)
6/5.4ns
Operating Supply Voltage (typ)
3.3V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
150mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with
11. Does not affect the state of the bank and acts as a NOP to that bank.
5. The following states must not be interrupted by any executable command; COMMAND
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regard-
INHIBIT or NOP commands must be applied on each positive clock edge during these states.
Refreshing:
Accessing mode
register:
Precharging all:
state for precharging.
less of bank.
auto precharge enabled and READs or WRITEs with auto precharge disabled.
Starts with registration of an AUTO REFRESH command and ends
when
idle state.
Starts with registration of a LMR command and ends when
has been met. After
idle state.
Starts with registration of a PRECHARGE ALL command and ends
when
43
t
t
RC is met. After
RP is met. After
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
MRD is met, the SDRAM will be in the all banks
t
t
RC is met, the SDRAM will be in the all banks
RP is met, all banks will be in the idle state.
128Mb: x4, x8, x16 SDRAM
©1999 Micron Technology, Inc. All rights reserved.
Operations
t
MRD