QT2032-EKG-1A2 Applied Micro Circuits Corporation, QT2032-EKG-1A2 Datasheet - Page 180
![no-image](/images/manufacturer_photos/0/0/70/applied_micro_circuits_corporation_sml.jpg)
QT2032-EKG-1A2
Manufacturer Part Number
QT2032-EKG-1A2
Description
Manufacturer
Applied Micro Circuits Corporation
Datasheet
1.QT2032-EKG-1A2.pdf
(220 pages)
Specifications of QT2032-EKG-1A2
Lead Free Status / RoHS Status
Supplier Unconfirmed
- Current page: 180 of 220
- Download datasheet (3Mb)
QT2022/32 - Data Sheet: DS3051
180
5:0
6
7
8
9
11:10
12
13
14
15
1. This bit is linked to an MDIO latched high diagnostic alarm register bit. A read of either register clears both.
3:0
7:4
11:8
15:12
Bit
Bit
XAUI Lane 0
Sync offset, RO
XAUI Lane 1
Sync offset, RO
XAUI Lane 2
Sync offset, RO
XAUI Lane 3
Sync offset, RO
Reserved, RO
XGXS Rx rate adjust underflow
1 = underflow
linked to 1.9003h.6
XGXS Rx rate adjust overflow
1 = overflow
linked to 1.9003h.6
XGXS Tx rate adjust underflow
1 = underflow
linked to 1.9004.2
XGXS Tx rate adjust overflow
1 = overflow
linked to 1.9004.2
Reserved, RO
XGXS Rx Rate Inserted Idle Flag, RO/LH
XGXS Rx Rate Removed Idle Flag, RO/LH
XGXS Tx Rate Inserted Idle Flag, RO/LH
XGXS Tx Rate Removed Idle Flag, RO/LH
PHY_XS Vendor Specific
AppliedMicro - Confidential & Proprietary
Register 4.C003h
1
1
, RO/LH
, RO/LH
1
1
, RO/LH
, RO/LH
Register 4.C002h
PHY_XS Vendor
Specific
XAUI Lane 0
Align offset, RO
XAUI Lane 1
Align offset, RO
XAUI Lane 2
Align offset, RO
XAUI Lane 3
Align offset, RO
PHY_XS Vendor Specific
Register 4.C004h
Revision 5.11