QT2032-EKG-1A2 Applied Micro Circuits Corporation, QT2032-EKG-1A2 Datasheet - Page 65

• Manufacturer Part Number: QT2032-EKG-1A2
• Manufacturer: Applied Micro Circuits Corporation

Specifications of QT2032-EKG-1A2

• Lead Free Status / RoHS Status: Supplier Unconfirmed

rx_flag
rx_flag is used to flag a DOM receive alarm.
rx_flag = {OR of (reg 1.A071.n ‘bit wise AND’ reg 1.9007.n) for n=0 to 7}
Table 25: rx_flag Alarm Registers
* rx_alarm bits 0 through 5 are read from the DOM device and mapped to registers 1.A071h.5:0. The function of
these bits is not specifically defined in the XENPAK MSA, but they are used in generating the rx_flag signal in order
to allow for vendor specific alarms to be defined. These alarms should be disabled via the associated MDIO regis-
ter bits 1.9007.5:0 when not is use.
TX_ALARM
TX_ALARM is used to indicate that a fault has occurred on the transmit path. TX_ALARM is the bitwise OR of the
receive path status register bits in register 1.9004h. TX_ALARM can be programmed to assert only when specific
receive path fault conditions are present. The programming is performed by writing to a mask register at address
1.9001h. The contents of register 1.9004h is AND’ed with register 1.9001h prior to application of the OR function to
generate the TX_ALARM signal.
tx_alarm = {OR of (reg 1.9004.n ‘bit wise AND’ reg 1.9001.n) for n=0..10}
Table 26: Transmit Alarm Registers (TX_ALARM)
Revision 5.11
Receive Optical Power High Alarm
Receive Optical Power Low Alarm
rx_flag alarm bits 0 through 5 *
PHY_XS transmit local
fault
tx_flag
PHY_XS transmit rate
error
PCS transmit local
fault
(MDIO 3.8.11)
Description
Description
NOT(TxXAUI Lane
Align)
(linked to 4.8.11)
bitwise OR of tx_flag register, 1.9006h
Transmit FIFO overflow/underflow error
(4.C002h.9 OR 4.C002h.8)
Transmit FIFO
overflow/underflow
error
(linked to 3.8.11)
LEGACY=0
AppliedMicro - Confidential & Proprietary
Alarm Definition
MDIO Status Register
1.A071h.7
1.A071h.6
1.A071h.5:0
NOT(TxXAUI CDR
lock<3:0>)
(linked to 4.8.11)
NOT(TxXAUI Lane
Sync) or NOT
(TxXAUI Lane Align)
(linked to 3.8.11)
(RO,LH)
LEGACY=1
1.9007h.7
1.9007h.6
1.9007h.5:0
1.9004.0
1.9004.1
1.9004.2
1.9004.3
16b hex
Register (R/W)
MDIO Enable
Register (RO)
MDIO Status
RO/LH
RO/LH
RO/LH
RO/LH
type
QT2022/32 - Data Sheet: DS3051
MDIO Enable Register default
0
0
0
1.9001.0
1.9001.1
1.9001.2
1.9001.3
16b hex
MDIO Enable Register (R/W)
LEGACY
value
=0
default
1
0
0
1
LEGACY
1
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