QT2032-EKG-1A2 Applied Micro Circuits Corporation, QT2032-EKG-1A2 Datasheet - Page 89

• Manufacturer Part Number: QT2032-EKG-1A2
• Manufacturer: Applied Micro Circuits Corporation

Specifications of QT2032-EKG-1A2

• Lead Free Status / RoHS Status: Supplier Unconfirmed

10.6 Two-byte Addressing of Peripheral I2C Devices
To allow a single device on the I2C bus to store the entire DOM and EEPROM memory space, the QT2022/32 can
be configured to support 64kB rather than 256 bytes within an I2C device. This requires 2 bytes rather than 1 for
the addressing within the I2C device. To enable 2-byte addressing, the LED2 pin must be held low during a hard
reset. The device address must be 1010000 as defined in the XENPAK MSA for the EEPROM.
The read/write cycle will now contain two 8-bit address bytes. The upper word address is the most significant.
When executing a read/write command to the EEPROM memory space, the first word address will be all 0’s. This
means that the first 256 bytes of memory (address range 0000 - 00FFh) in the peripheral I2C device must be
reserved for the EEPROM memory. A sample 8 byte page write transaction to the EEPROM space is shown in
Figure 32. A sample 8 byte page read transaction to the EEPROM space is shown in Figure 33.
When performing a read/write command to the DOM memory space, the upper address byte will specify the base
address of the equivalent DOM memory in the peripheral I2C device. The lower three bits of this word are taken
from the ‘DOM capability’ register 1.807Ah, bits 2:0. The upper 5 bits are set by MDIO register bits 1.C023h.4:0
(default 0b00000). A sample 8 byte page write transaction to the DOM space is shown in Figure 34. A sample 8
byte page read transaction to the DOM space is shown in Figure 35.
In this mode, the QT2022/32 supports the same read and write commands as with standard 8-bit addressing. The
commands are initiated in the same manner.
10.6.1 Behavior on Startup/Reset
On startup or reset, the QT2022/32 will follow the boot sequence shown in figure 36 on page 92. The QT2022/32
will first initialize the bus and then pause for 250ms. The chip will then automatically read the NVR memory space.
The secondary EEPROM memories and the DOM memory space are then read, if enabled.
Bus Initialization
The QT2022/32 initializes the two wire interface by sending 9 STOP conditions on the bus. This clears any transac-
tions that are in progress on the bus. In particular, this prevents bus conflicts if any previous transactions are
interrupted by reset events.
Reset Behavior with Two-Byte Addressing
This behavior is not changed when two-byte addressing is enabled. The value of MDIO register bits 1.C023h.4:0
will revert to their default value on startup or reset. Therefore, the upper address byte will be in the range 0x01 to
0x07. Thus, the DOM memory space must be located in the lower 2kB of I2C device memory for the automatic
read to work properly on startup/reset.
Figure 32: 2-Byte Addressing for EEPROM Write Cycle Timing
Revision 5.11
S 1 0
S
T
A
R
T
slave address
1
0
0 0 0
W
R
I
T
E
0
AppliedMicro - Confidential & Proprietary
A
A
C
K
0
0
address byte
00000000
0 0
upper
0
0
0 0
A
A
C
K
address byte
lower
A
A
C
K
d7 d6 d1 d0
QT2022/32 - Data Sheet: DS3051
data byte 0
A
A
C
K
data bytes 1 - 7
d7 d6 d1 d0
EEPROM
PHY
A
A
C
K
P
S
T
O
P
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