IDT77V1264L200PGI IDT, Integrated Device Technology Inc, IDT77V1264L200PGI Datasheet - Page 2

• Manufacturer Part Number: IDT77V1264L200PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1264L200PGI

• Number Of Channels: 4
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.47V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Applications
77V1264L200 Overview
standard for 25.6Mbps ATM network communications as defined by
ATM Forum document af-phy-040.000 and ITU-T I.432.5. The physical
layer is divided into a Physical Media Dependent sub layer (PMD) and
Transmission Convergence (TC) sub layer. The PMD sub layer includes
the functions for the transmitter, receiver and clock recovery for opera-
tion across 100 meters of category 3 and 5 unshielded twisted pair
(UTP) cable. This is referred to as the Line Side Interface. The TC sub
layer defines the line coding, scrambling, data framing and synchroniza-
tion.
device (such as a switch core or SAR). This cell level interface is config-
urable as either an 8-bit Utopia Level 1 Multi-PHY, 16-bit Utopia Level 2,
or four 4-bit DPI interface, as determined by two MODE pins. This is
referred to as the PHY-ATM Interface. The pinout and front page block
diagram are based on the Utopia 2 configuration. Table 3 shows the
corresponding pin functions for the other two modes, and Figure 2 and
Figure 3 show functional block diagrams.
register compatibility with it. The 77V1264L200, however, has additional
register features, and also duplicates most of its registers to provide
significant independence between the four ports.
This is an 8-bit muxed address and data bus, controlled by a conven-
tional asynchronous read/write handshake.
marker, and provide LED indication of receive and transmit status.
Auto-Synchronization and Good Signal Indica-
tion
that allow it to achieve 4b/5b symbol framing on any valid data stream.
This is an improvement on earlier products which could frame only on
the escape symbol, which occurs only in start-of-cell or 8kHz (X8) timing
marker symbol pairs.
the 77V1264L200 receive section to achieve symbol framing and prop-
erly indicate receive signal status, even in the absence of ATM cells or
8kHz (X8) timing markers in the receive data stream. A state machine
monitors the received symbols and asserts the “Good Signal” status bit
when a valid signal is being received. “Good Signal” is deasserted and
the receive FIFO is disabled when the signal is lost. This is sometimes
referred to as Loss of Signal (LOS).
Operation at Speeds Above 25 Mbps
77V1264L200 can be operated at a range of data rates, up to 204.8
IDT77V1264L200
The 77V1264L200 is a four port implementation of the physical layer
On the other side, the 77V1264L200 interfaces to an ATM layer
The 77V1264L200 is based on the 77105, and maintains significant
Access to these status and control registers is through the utility bus.
Additional pins permit insertion and extraction of an 8kHz timing
The 77V1264L200 features a new receiver synchronization algorithm
ATM25 transceivers always transmit valid 4b/5b symbols, allowing
In addition to operation at the standard rate of 25.6 Mbps, the
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Up to 204.8Mbps backplane transmission
Rack-to-rack short links
ATM Switches
2 of 49
Mbps, as shown in Table 3. For 204.8Mbps data rate applications,
ST6200T magnetics from Pulse Engineering can be used. These
magnetics have been tested to work over 10 meters of UTP 5 cable at
204.8Mbps. The rate is determined by the frequency of the OSC clock,
multiplied by the internal PLL clock multiplier factor (1x, 2x or 4x) as
determined in the Enhanced Control 2 Registers. Although the OSC
clock frequency is common to all ports of the PHY, the clock multiplier
factor can be set individually for each port. As an example, with a 64
MHz oscillator, this allows some ports to operate at 51.2 Mbps while
other ports are simultaneously operating at 204.8 Mbps.
pin requires that the RXREF Pulse Width Select field in the LED Driver
and HEC Status/Control Registers be programmed to a value greater
than the default of 1 cycle.
Diagnostic Control Registers works only when the clock multiplier is 1x.
For higher multiples, the PHY loopback mode (01) with clock recovery
must be used.
exactly the same as the basic 25.6 Mbps configuration. The scrambling
and encoding are unchanged.
at with a 32MHz or 64MHz oscillator. Note that any oscillator frequency
between 32MHz and 64MHz can be used. For example, if a 48MHz
oscillator is used and the multiplier is set to 4x, the data rate would be
153.6Mbps.
Clock (OSC)
Reference
When operating at clock multiples other than 1x, use of the RXREF
Also, the PHY loopback mode without clock recovery (10) in the
Except as noted above, these higher speed configurations operate
Table 1 shows some of the different data rates the PHY can operate
32 MHz
64 MHz
Table 1 200 Speed Grade Option
Clock Multiplier
(Enhanced Control 2
Control Bits
Registers)
00 (1x)
01 (2x)
10 (4x)
00 (1x)
01 (2x)
10 (4x)
Line Bit
(MHz)
Rate
128
128
256
December 2004
32
64
64
(Mbps)
Data
Rate
102.4
102.4
204.8
25.6
51.2
51.2