IDT77V1264L200PGI IDT, Integrated Device Technology Inc, IDT77V1264L200PGI Datasheet - Page 6

• Manufacturer Part Number: IDT77V1264L200PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1264L200PGI

• Number Of Channels: 4
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.47V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Signal Name
RXCLAV[3:0]
RXCLK
RXDATA[7:0]
RXEN[3:0]
RXPARITY
RXSOC
TXCLAV[3:0]
TXCLK
TXDATA[7:0]
TXEN[3:0]
TXPARITY
TXSOC
Signal Name
DPICLK
Pn_RCLK
Pn_RD[3:0]
Pn_RFRM
Pn_TCLK
Pn_TD[3:0]
Pn_TFRM
IDT77V1264L200
Pin Number
64, 65, 66, 54
46
69, 70, 71, 72, 73, 74, 75, 76 Out
51, 49, 48, 47
58
55
39, 40, 41, 42
43
24, 23, 22, 21, 20, 19, 18, 17 In
27, 26, 25, 34
33
35
Pin Number
43
52, 51, 49, 48
59, 60, 61, 62, 63, 64, 65,
66, 69, 70, 71, 72, 73, 74,
75, 76
53, 58, 54, 55
37, 39, 40, 41
32, 31, 30, 29, 28, 27, 26,
25, 24, 23, 22, 21, 20, 19,
18, 17
36, 33, 34, 35
8-BIT UTOPIA Level 1 Signals (MODE[1:0] = 01)
I/O
Out
In
In
Out
Out
Out
In
In
In
In
I/O
In
In
Out
Out
Out
In
In
Signal Description
Utopia 1 Receive Cell Available. Indicates the cell available status of the respective port. It is asserted when
a full cell is available for retrieval from the receive FIFO.
Utopia 1 Receive Clock. This is a free running clock input.
Utopia 1 Receive Data. When one of the four ports is selected, the 77V1264L200 transfers received cells to
an ATM device across this bus. Bit 5 in the Diagnostic Control Registers determines whether RXDATA tri-
states when RXEN[3:0] are high. Also see RXPARITY.
Utopia 1 Receive Enable. Driven by an ATM device to indicate its ability to receive data across the RXDATA
bus. One for each port
Utopia 1 Receive Data Parity. Odd parity over RXDATA[7:0].
Utopia 1 Receive Start of Cell. Asserted coincident with the first word of data for each cell on RXDATA. Tri-
statable as determined by bit 5 in the Diagnostic Control Registers.
Utopia 1 Transmit cell Available. Indicates the availability of room in the transmit FIFO of the respective port
for a full cell.
Utopia 1 Transmit Clock. This is a free running clock input.
Utopia 1 Transmit Data. An ATM device transfers cells across the bus to the 77V1264L200 for transmission.
Also see TXPARITY.
Utopia 1 Transmit Enable. Driven by an ATM device to indicate it is transmitting data across the TXDATA
bus. One for each port.
Utopia 1 Transmit Data Parity. Odd parity across TXDATA[7:0]. Parity is checked and errors are indicated in
the Interrupt Status Registers, as enabled in the Master Control Registers. No other action is taken in the
event of an error. Tie high or low if unused.
Utopia 1 Transmit Start of Cell. Asserted coincident with the first word of data for each cell on TXDATA.
DPI Mode Signals (MODE[1:0] = 10)
Signal Description
DPI Source Clock for Transmit. This is the free-running clock used as the source to generate Pn_TCLK.
DPI Port ’n’ Receive Clock. Pn_RCLK is cycled to indicate that the interfacing device is ready to receive a
nibble of data on Pn_RD[3:0] of port ’n’.
DPI Port ’n’ Receive Data. Cells received on port ’n’ are passed to the interfacing device across this bus.
Each port has its own dedicated bus.
DPI Port ’n’ Receive Frame. Pn_RFRM is asserted for one cycle immediately preceding the transfer of each
cell on Pn_RD[3:0].
DPI Port ’n’ Transmit Clock. Pn_TCLK is derived from DPICLK and is cycled when the respective port is
ready to accept another 4 bits of data on Pn_TD[3:0].
DPI Port ’n’ Transmit Data. Cells are passed across this bus to the PHY for transmission on port ’n’. Each
port has its own dedicated bus.
DPI Port ’n’ Transmit Frame. Start of cell signal which is asserted for one cycle immediately preceding the
first 4 bits of each cell on Pn_TD[3:0].
Table 2 Signal Descriptions (Part 3 of 3)
6 of 49
December 2004