IDT77V1264L200PGI IDT, Integrated Device Technology Inc, IDT77V1264L200PGI Datasheet - Page 27

• Manufacturer Part Number: IDT77V1264L200PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1264L200PGI

• Number Of Channels: 4
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.47V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Control and Status Interface
registers within the IDT77V1264L200. These registers are used to select
desired operating characteristics and functions, and to communicate
status to external systems.
bus (AD[7:0]) where the register address is latched via the Address
Latch Enable (ALE) signal.
register read is performed as follows:
signalling conditions which are useful both during ‘normal’ operation,
and as diagnostic aids. Refer to the Status and Control Register List
section.
Registers. When this bit is cleared (set to 0), interrupt signalling is
prevented on the respective port. The Interrupt Mask Registers allow
individual masking of different interrupt sources. Additional interrupt
IDT77V1264L200
Utility Bus
The Utility Bus is a byte-wide interface that provides access to the
The Utility Bus is implemented using a multiplexed address and data
The Utility Bus interface is comprised of the following pins:
AD[7:0], ALE, CS, RD, WR
Read Operation
Refer to the Utility Bus timing waveforms in Figures 43 - 44. A
1. Initial condition:
2. Set up register address:
3. Read register data:
Write Operation
A register write is performed as described below:
1. Initial condition:
2. Set up register address:
3. Write data:
Interrupt Operations
The IDT77V1264L200 provides a variety of selectable interrupt and
Overall interrupt control is provided via bit 0 of the Master Control
– RD, WR, CS not asserted (logic 1)
– ALE not asserted (logic 0)
– place desired register address on AD[7:0]
– set ALE to logic 1;
–
– Remove register address data from AD[7:0]
– assert CS by setting to logic 0;
– assert RD by setting to logic 0
– wait minimum pulse width time (see AC specifications)
– RD, WR, CS not asserted (logic 1)
– ALE not asserted (logic 0)
– place desired register address on AD[7:0]
– set ALE to logic 1;
– latch this address by setting ALE to logic 0.
– place data on AD[7:0]
– assert CS by setting to logic 0;
– assert WR (logic 0) for minimum time (according to timing
specification); reset WR to logic 1 to complete register write
cycle.
latch this address by setting ALE to logic 0.
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signal control is provided by bit 5 of the Master Control Registers. When
this bit is set (=1), receive cell errors will be flagged via interrupt signal-
ling and all other interrupt conditions are masked. These errors include:
clearing bit 5 in the Master Control Registers. INT (pin 85) will go to a
low state when an interrupt condition is detected. The external system
should then interrogate the 77V1264L200 to determine which one (or
more) conditions caused this flag, and reset the interrupt for further
occurrences. This is accomplished by reading the Interrupt Status
Registers. Decoding the bits in these bytes will tell which error condition
caused the interrupt. Reading these registers also:
problems.
As an example, the RXLED outputs are described in the truth table:
provide for a two-LED condition indicator. These could also be different
colors to provide simple status indication at a glance. (The minimum
value for R should be 330 ).
!
!
Normal interrupt operations are performed by setting bit 0 and
This leaves the interrupt system ready to signal an alarm for further
LED Control and Signalling
The LED outputs provide bi-directional LED drive capability of 8 mA.
As illustrated in the following drawing, this could be connected to
LED Indicator
TXLED Truth Table
RxLED(3:0)
TxLED(3:0)
!
!
!
clears the (sticky) interrupt status bits in the registers that are read
resets INT
Bad receive HEC
Short (fewer than 53 bytes) cells
Received cell symbol error
Cells being transmitted
Cells not being transmitted High
Cells being received
Cells not being received High
State
State
R
R
3.3V
Low
Pin Voltage
not being received or
Low
(Indicates: Cells are
Pin Voltage
being received or
(Indicates: Cells
transmitted)
transmitted)
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