IDT77V1264L200PGI IDT, Integrated Device Technology Inc, IDT77V1264L200PGI Datasheet - Page 24

• Manufacturer Part Number: IDT77V1264L200PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1264L200PGI

• Number Of Channels: 4
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.47V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

DPI Interface Option
The biggest difference between the DPI configurations and the UTOPIA
configurations is that each channel has its own DPI interface. Each
interface has a 4-bit data path, a clock and a start-of-cell signal, for both
the transmit direction and the receive direction. Therefore, each signal is
point-to-point, and none of these signals has high-Z capability. Addition-
ally, there is one master DPI clock input (DPICLK) into the 77V1254L25
which is used as a source for the DPI transmit clock outputs. DPI is a
cell-based transfer scheme like Utopia Level 2, whereas UTOPIA Level
1 transfers can be either byte- or cell-based.
as easy to connect two PHYs back-to-back as it is to connect a PHY to a
switch fabric chip. In contrast, Utopia is asymmetrical. Note that for the
77V1254L25 the nomenclature "transmit" and "receive" is used in the
naming of the DPI signals, whereas other devices may use more
generic "in" and "out" nomenclature for their DPI signals.
signals for channel number "n":
start-of-cell signal (Pn_TFRM) for one clock cycle, one clock prior to
driving the first nibble of the cell on Pn_TD[3:0]. Once the ATM side has
begun sending a cell, it is prepared to send the entire cell without inter-
ruption. The 77V1254L25 drives the transmit DPI clocks (Pn_TCLK)
back to the ATM device, and can modulate (gap) it to control the flow of
data. Specifically, if it cannot accept another nibble, the 77V1254L25
disables Pn_TCLK and does not generate another rising edge until it
has room for the nibble. Pn_TCLK are derived from the DPICLK free
running clock source.
the 77V1254L25 driving the data and start-of-cell signals while receiving
Pn_RCLK as an input.
transferred in 106 cycles. Figure 22 shows the sequence of that data
transfer. igures 23 through 31 show how the handshake operates.
IDT77V1264L200
The DPI interface is relatively new and worth additional description.
Another unique aspect of DPI is that it is a symmetrical interface. It is
The DPI signals are summarized below, where "Pn_" refers to the
In the transmit direction (ATM to PHY), the ATM layer device asserts
The DPI protocol is exactly symmetrical in the receive direction, with
The DPI data interface is four bits, so the 53 bytes of an ATM cell are
DPICLK
Pn_TCLK
Pn_TD[3:0]
Pn_TFRM
Pn_RCLK
Pn_RD[3:0]
Pn_RFRM
input to PHY
PHY to ATM
ATM to PHY
ATM to PHY
ATM to PHY
PHY to ATM
PHY to ATM
24 of 49
Figure 22 DPI Data Format and Sequence
First
Last
Bit 3
Payload byte 47, (8:5)
Payload byte 47, (4:1)
Payload byte 48, (8:5)
Payload byte 48, (4:1)
Payload byte 1, (8:5)
Payload byte 1, (4:1)
Header byte 1, (8:5)
Header byte 1, (4:1)
Header byte 2, (8:5)
Header byte 2, (4:1)
Header byte 3, (8:5)
Header byte 3, (4:1)
Header byte 4, (8:5)
Header byte 4, (4:1)
Header byte 5, (8:5)
Header byte 5, (4:1)
Bit 0
December 2004