LAN9312-NU Standard Microsystems (SMSC), LAN9312-NU Datasheet - Page 128
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LAN9312-NU
Manufacturer Part Number
LAN9312-NU
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9312-NU.pdf
(458 pages)
Specifications of LAN9312-NU
Number Of Primary Switch Ports
2
Operating Supply Voltage (typ)
3.3V
Fiber Support
No
Phy/transceiver Interface
MII
Power Supply Type
Analog
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9312-NU
Manufacturer:
Microchip Technology
Quantity:
10 000
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Revision 1.7 (06-29-10)
9.8.5
9.8.6
9.8.6.1
BITS
6:3
9
8
7
2
1
0
Late Collision. When set, indicates that the packet transmission was aborted after the collision
window of 64 bytes.
Excessive Collisions. When set, this bit indicates that the transmission was aborted after 16
collisions while attempting to transmit the current packet.
Reserved. This bit is reserved. Always write zeros to this field to guarantee future compatibility.
Collision Count. This counter indicates the number of collisions that occurred before the packet was
transmitted. It is not valid when excessive collisions (bit 8) is also set.
Excessive Deferral. If the deferred bit is set in the control register, the setting of the excessive
deferral bit indicates that the transmission has ended because of a deferral of over 24288 bit times
during transmission.
Reserved. This bit is reserved. Always write zeros to this field to guarantee future compatibility
Deferred. When set, this bit indicates that the current packet transmission was deferred.
Calculating Actual TX Data FIFO Usage
The following rules are used to calculate the actual TX Data FIFO space consumed by a TX Packet:
Transmit Examples
TX Example 1
In this example a single, 111-Byte Ethernet packet will be transmitted. This packet is divided into three
buffers. The three buffers are as follows:
Buffer 0:
Buffer 1:
Buffer 2:
TX command 'A' is stored in the TX Data FIFO for every TX buffer
TX command 'B' is written into the TX Data FIFO when the First Segment (FS) bit is set in TX
command 'A'
Any DWORD-long data added as part of the “Data Start Offset” is removed from each buffer before
the data is written to the TX Data FIFO. Any data that is less than 1 DWORD is passed to the TX
Data FIFO.
Payload from each buffer within a Packet is written into the TX Data FIFO.
Any DWORD-long data added as part of the End Padding is removed from each buffer before the
data is written to the TX Data FIFO. Any end padding that is less than 1 DWORD is passed to the
TX Data FIFO
7-Byte “Data Start Offset”
79-Bytes of payload data
16-Byte “Buffer End Alignment”
0-Byte “Data Start Offset”
15-Bytes of payload data
16-Byte “Buffer End Alignment”
10-Byte “Data Start Offset”
17-Bytes of payload data
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
128
DESCRIPTION
SMSC LAN9312
Datasheet
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