LAN9312-NU Standard Microsystems (SMSC), LAN9312-NU Datasheet - Page 64
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LAN9312-NU
Manufacturer Part Number
LAN9312-NU
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9312-NU.pdf
(458 pages)
Specifications of LAN9312-NU
Number Of Primary Switch Ports
2
Operating Supply Voltage (typ)
3.3V
Fiber Support
No
Phy/transceiver Interface
MII
Power Supply Type
Analog
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9312-NU
Manufacturer:
Microchip Technology
Quantity:
10 000
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Revision 1.7 (06-29-10)
6.4.1.1
6.4.1.2
6.4.1.3
6.4.1.4
6.4.1.5
6.4.1.6
6.4.1.7
Learning/Aging/Migration
The ALR adds new MAC addresses upon ingress along with the associated receive port.
If the source MAC address already exists, the entry is refreshed. This action serves two purposes.
First, if the source port has changed due to a network reconfiguration (migration), it is updated.
Second, each instance the entry is refreshed, the aging status bit is set, keeping the entry active.
Learning can be disabled per port via the Enable Learning on Ingress field of the
Ingress Configuration Register
During each aging period, the ALR scans the learned MAC addresses. For entries which have the
aging status bit set, the ALR simply clears the bit. As mentioned above, if a MAC address is
subsequently refreshed, the aging bit will be set again and the process would repeat. If a learned entry
already had its aging status bit cleared (by a previous scan), the ALR will instead remove the learned
entry. Therefore, if two scans occur before a MAC address is refreshed, the entry will be aged and
removed. Each aging period is approximately 5 minutes. Therefore an entry will be aged and removed
at a minimum of 5 minutes, and a maximum of 10 minutes.
Static Entries
If a MAC address entry is manually added by the host CPU, it can be (and typically is) marked as
static. Static entries are not subjected to the aging process. Static entries also cannot be changed by
the learning process (including migration).
Multicast Pruning
The destination port that is returned as a result of a destination MAC address lookup may be a single
port or any combination of ports. The latter is used to setup multicast address groups. An entry with
a multicast MAC address would be entered manually by the host CPU with the appropriate destination
port(s). Typically, the Static bit should also be set to prevent automatic aging of the entry.
Address Filtering
Filtering can be performed on a destination MAC address. Such an entry would be entered manually
by the host CPU with the Filter bit active. Typically, the Static bit should also be set to prevent
automatic aging of the entry.
Spanning Tree Port State Override
A special spanning tree port state override setting can be applied to MAC address entries. When the
host CPU manually adds an entry with both the Static and Age bits set, packets with a matching
destination address will bypass the spanning tree port state and will be forwarded. This feature is
typically used to allow the reception of the BPDU packets while a port is in the non-forwarding state.
Refer to
MAC Destination Address Lookup Priority
I f
(SWE_GLOBAL_INGRSS_CFG), the transmit priority for static MAC address entries is taken from the
associated data of that entry.
Host Access
The ALR contains a learning engine that is used by the host CPU to add, delete, and modify the MAC
Address Table. This engine is accessed by using the
(SWE_ALR_CMD),
Engine ALR Write Data 0 Register
Register
e n a b l e d
Section 6.4.5, "Spanning Tree Support," on page 70
(SWE_ALR_WR_DAT_1).
i n
Switch Engine ALR Command Status Register
t h e
S w i t c h
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
(SWE_PORT_INGRSS_CFG).
DATASHEET
(SWE_ALR_WR_DAT_0), and
E n g i n e
64
G l o b a l
Switch Engine ALR Command Register
I n g r e s s
for additional details.
Switch Engine ALR Write Data 1
(SWE_ALR_CMD_STS),
C o n f i g u r a t i o n
Switch Engine Port
SMSC LAN9312
R e g i s t e r
Datasheet
Switch
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