LAN9312-NU Standard Microsystems (SMSC), LAN9312-NU Datasheet - Page 320
![no-image](/images/manufacturer_photos/0/6/632/standard_microsystems__smsc__sml.jpg)
LAN9312-NU
Manufacturer Part Number
LAN9312-NU
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9312-NU.pdf
(458 pages)
Specifications of LAN9312-NU
Number Of Primary Switch Ports
2
Operating Supply Voltage (typ)
3.3V
Fiber Support
No
Phy/transceiver Interface
MII
Power Supply Type
Analog
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9312-NU
Manufacturer:
Microchip Technology
Quantity:
10 000
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Revision 1.7 (06-29-10)
14.5.1.3
BITS
31:9
8:7
4:3
6
5
2
1
0
RESERVED
RESERVED
Note:
Buffer Manager Interrupt Mask (BM)
When set, prevents the generation of switch fabric interrupts due to the
Buffer Manager via the
(BM_IPR). The status bits in the SW_IPR register are not affected.
Switch Engine Interrupt Mask (SWE)
When set, prevents the generation of switch fabric interrupts due to the
Switch Engine via the
The status bits in the SW_IPR register are not affected.
RESERVED
Note:
Port 2 MAC Interrupt Mask (MAC_2)
When set, prevents the generation of switch fabric interrupts due to the Port
2 MAC via the MAC_IPR_2 register (see
The status bits in the SW_IPR register are not affected.
Port 1 MAC Interrupt Mask (MAC_1)
When set, prevents the generation of switch fabric interrupts due to the Port
1 MAC via the MAC_IPR_1 register (see
The status bits in the SW_IPR register are not affected.
Port 0 MAC Interrupt Mask (MAC_MII)
When set, prevents the generation of switch fabric interrupts due to the Port
0 MAC via the MAC_IPR_MII register (see
The status bits in the SW_IPR register are not affected.
Switch Global Interrupt Mask Register (SW_IMR)
This read/write register contains the global interrupt mask for the switch fabric interrupts. All switch
related interrupts in the
register. An interrupt is masked by setting the corresponding bit of this register. Clearing a bit will
unmask the interrupt. When an unmasked switch fabric interrupt is generated in the
Interrupt Pending Register
Status Register
These bits must be written as 11b
These bits must be written as 11b
Register #:
(INT_STS). Refer to
Switch Engine Interrupt Pending Register
Buffer Manager Interrupt Pending Register
Switch Global Interrupt Pending Register (SW_IPR)
0004h
DESCRIPTION
(SW_IPR), the interrupt will trigger the SWITCH_INT bit in the
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
Chapter 5, "System Interrupts," on page 49
Section 14.5.2.44, on page
Section 14.5.2.44, on page
Section 14.5.2.44, on page
320
Size:
(SWE_IPR).
32 bits
365).
365).
365).
TYPE
may be masked via this
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
for more information.
SMSC LAN9312
Switch Global
DEFAULT
11b
11b
Datasheet
1b
1b
1b
1b
1b
Interrupt
-
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