LAN9312-NU Standard Microsystems (SMSC), LAN9312-NU Datasheet - Page 143
![no-image](/images/manufacturer_photos/0/6/632/standard_microsystems__smsc__sml.jpg)
LAN9312-NU
Manufacturer Part Number
LAN9312-NU
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9312-NU.pdf
(458 pages)
Specifications of LAN9312-NU
Number Of Primary Switch Ports
2
Operating Supply Voltage (typ)
3.3V
Fiber Support
No
Phy/transceiver Interface
MII
Power Supply Type
Analog
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9312-NU
Manufacturer:
Microchip Technology
Quantity:
10 000
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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
10.2.2.5
A
C
K
D
7
D
6
Data Byte
D
5
Data Cycle
D
4
Sequential reads are used by the EEPROM Loader. Refer to
additional information.
For a register level description of a read operation, refer to
Operation," on page
I
Following the device addressing, a data byte may be written to the EEPROM by outputting the data
after receiving the acknowledge from the EEPROM. The data byte is acknowledged by the EEPROM
slave and the I
send an acknowledge, then the sequence is aborted and the EPC_TIMEOUT bit in the
Command Register (E2P_CMD)
Following the data byte write cycle, the I
write is finished. A start condition is sent followed by a control byte with a control code of 1010b,
chip/block select bits low, and the R/~W bit low. If the EEPROM is finished with the byte write, it will
respond with an acknowledge. Otherwise, it will respond with a no-acknowledge and the I
will repeat the poll. If the acknowledge does not occur within 30mS, a time-out occurs. Once the I
master receives the acknowledge, it concludes by sending a start condition, followed by a stop
condition, which will place the EEPROM into standby.
Figure 10.4
D
3
For a register level description of a write operation, refer to
Operation," on page
2
C EEPROM Byte Writes
D
2
D
1
D
0
A
C
K
illustrates typical I
P
2
S 1 0 1 0
C master finishes the write cycle with a stop condition. If the EEPROM slave fails to
138.
138.
Control Byte
Poll Cycle
Chip / Block
Select Bits
Figure 10.6 I
0 0 0
2
C EEPROM byte write.
is set.
DATASHEET
0
R/~W
2
C
A
K
C EEPROM Byte Write
2
S 1 0 1 0
C master will poll the EEPROM to determine when the byte
143
Control Byte
Poll Cycle
Chip / Block
Select Bits
0 0 0
0
R/~W
Section 10.2.4, "EEPROM Loader"
Section 10.2.1, "EEPROM Controller
Section 10.2.1, "EEPROM Controller
A
C
K
...
S 1 0 1 0
Control Byte
Poll Cycle
Chip / Block
Select Bits
Revision 1.7 (06-29-10)
0 0 0
2
0
Conclude
R/~W
EEPROM
C master
A
C
K
S P
for
2
C
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