LAN9312-NU Standard Microsystems (SMSC), LAN9312-NU Datasheet - Page 136
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LAN9312-NU
Manufacturer Part Number
LAN9312-NU
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9312-NU.pdf
(458 pages)
Specifications of LAN9312-NU
Number Of Primary Switch Ports
2
Operating Supply Voltage (typ)
3.3V
Fiber Support
No
Phy/transceiver Interface
MII
Power Supply Type
Analog
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9312-NU
Manufacturer:
Microchip Technology
Quantity:
10 000
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Revision 1.7 (06-29-10)
9.9.4
9.9.5
BITS
7
6
5
4
3
2
1
0
Frame Too Long. When set, this bit indicates that the frame length exceeds the maximum Ethernet
specification of 1518 bytes. This is only a frame too long indication and will not cause the frame
reception to be truncated.
Collision Seen. When set, this bit indicates that the frame has seen a collision after the collision
window. This indicates that a late collision has occurred.
Frame Type. When set, this bit indicates that the frame is an Ethernet-type frame (Length/Type field
in the frame is greater than 1500). When reset, it indicates the incoming frame was an 802.3 type
frame. This bit is not set for Runt frames less than 14 bytes.
Receive Watchdog time-out. When set, this bit indicates that the incoming frame is greater than
2048 bytes through 2560 bytes, therefore expiring the Receive Watchdog Timer.
MII Error. When set, this bit indicates that a receive error was detected during frame reception.
Dribbling Bit. When set, this bit indicates that the frame contained a non-integer multiple of 8 bits.
This error is reported only if the number of dribbling bits in the last byte is at least 3 in the 10 Mbps
operating mode. This bit will not be set when the collision seen bit[6] is set. If set and the CRC error
bit is [1] reset, then the packet is considered to be valid.
CRC Error. When set, this bit indicates that a CRC error was detected. This bit is also set when the
RX_ER pin is asserted during the reception of a frame even though the CRC may be correct. This bit
is not valid if the received frame is a Runt frame, or a late collision was detected or when the
Watchdog Time-out occurs.
Reserved. These bits are reserved. Reads 0
Stopping and Starting the Receiver
To stop the receiver, the host must clear the RXEN bit in the
When the receiver is halted, the RXSTOP_INT will be pulsed and reflected in the
Register
The host must re-enable the receiver by setting the RXEN bit.
Receiver Errors
If the Receiver Error (RXE) flag is asserted in the
the receiver will continue operation. RX Error (RXE) will be asserted under the following conditions:
It is the duty of the host to identify and resolve any error conditions.
A host underrun of RX Data FIFO
A host underrun of the RX Status FIFO
An overrun of the RX Status FIFO
(INT_STS). Once stopped, the host can optionally clear the RX Status and RX Data FIFOs.
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
136
DESCRIPTION
Interrupt Status Register (INT_STS)
Host MAC Control Register
Interrupt Status
for any reason,
SMSC LAN9312
(HMAC_CR).
Datasheet
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