LAN9312-NU Standard Microsystems (SMSC), LAN9312-NU Datasheet - Page 52
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LAN9312-NU
Manufacturer Part Number
LAN9312-NU
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9312-NU.pdf
(458 pages)
Specifications of LAN9312-NU
Number Of Primary Switch Ports
2
Operating Supply Voltage (typ)
3.3V
Fiber Support
No
Phy/transceiver Interface
MII
Power Supply Type
Analog
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9312-NU
Manufacturer:
Microchip Technology
Quantity:
10 000
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Revision 1.7 (06-29-10)
5.2.3
5.2.4
5.2.5
Ethernet PHY Interrupts
The Port 1 and Port 2 PHYs each provide a set of identical interrupt sources. The top-level PHY_INT1
(bit 26) and PHY_INT2 (bit 27) of the
P H Y i n t e r r u p t e v e n t o c c u r r e d i n t h e
(PHY_INTERRUPT_SOURCE_x).
Port 1 and Port 2 PHY interrupts are enabled/disabled via their respective
Register
via the
Port 2 PHYs are each capable of generating unique interrupts based on the following events:
In order for a Port 1 or Port 2 interrupt event to trigger the external IRQ interrupt pin, the desired PHY
interrupt event must be enabled in the corresponding
(PHY_INTERRUPT_MASK_x), the PHY_INT1(Port 1 PHY) and/or PHY_INT2(Port 2 PHY) bits of the
Interrupt Enable Register (INT_EN)
of the
For additional details on the Ethernet PHY interrupts, refer to
page
GPIO Interrupts
Each GPIO[11:0] of the LAN9312 is provided with its own interrupt. The top-level GPIO (bit 12) of the
Interrupt Status Register (INT_STS)
General Purpose I/O Interrupt Status and Enable Register
Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)
and status of each GPIO[11:0] interrupt.
In order for a GPIO interrupt event to trigger the external IRQ interrupt pin, the desired GPIO interrupt
must be enabled in the
(GPIO_INT_STS_EN), bit 12 (GPIO_EN) of the
IRQ output must be enabled via bit 8 (IRQ_EN) of the
For additional details on the GPIO interrupts, refer to
Host MAC Interrupts
The top-level
status and enabling/disabling of multiple Host MAC related interrupts. All Host MAC interrupts are
monitored and configured directly within these two registers. The following Host MAC related interrupt
events are supported:
ENERGYON Activated
Auto-Negotiation Complete
Remote Fault Detected
Link Down (Link Status Negated)
Auto-Negotiation LP Acknowledge
Parallel Detection Fault
Auto-Negotiation Page Received
TX Stopped
RX Stopped
RX Dropped Frame Counter Halfway
TX IOC
RX DMA
94.
Interrupt Configuration Register
Port x PHY Interrupt Source Flags Register
(PHY_INTERRUPT_MASK_x). The source of a PHY interrupt can be determined and cleared
Interrupt Status Register
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
General Purpose I/O Interrupt Stat us and Enable Regist er
DATASHEET
must be set, and IRQ output must be enabled via bit 8 (IRQ_EN)
provides indication that a GPIO interrupt event occurred in the
(INT_STS), and
(IRQ_CFG).
Interrupt Status Register (INT_STS)
52
P o r t x P H Y I n t e r r u p t S o u r c e F l a g s R e g i s t e r
Interrupt Enable Register (INT_EN)
(PHY_INTERRUPT_SOURCE_x). The Port 1 and
Section 13.2.2, "GPIO Interrupts," on page
Interrupt Enable Register (INT_EN)
Interrupt Configuration Register
Port x PHY Interrupt Mask Register
(GPIO_INT_STS_EN). The
Section 7.2.8.1, "PHY Interrupts," on
provides enabling/disabling
Port x PHY Interrupt Mask
provides indication that a
must be set, and
SMSC LAN9312
(IRQ_CFG).
provide the
Datasheet
General
163.
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