LAN9312-NU Standard Microsystems (SMSC), LAN9312-NU Datasheet - Page 141
![no-image](/images/manufacturer_photos/0/6/632/standard_microsystems__smsc__sml.jpg)
LAN9312-NU
Manufacturer Part Number
LAN9312-NU
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9312-NU.pdf
(458 pages)
Specifications of LAN9312-NU
Number Of Primary Switch Ports
2
Operating Supply Voltage (typ)
3.3V
Fiber Support
No
Phy/transceiver Interface
MII
Power Supply Type
Analog
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9312-NU
Manufacturer:
Microchip Technology
Quantity:
10 000
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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
10.2.2.2
S 1 0 1 0
Control Byte
Chip / Block
EE_SDA
Select Bits
EE_SCL
Single Byte Addressing
A
1
0
Figure 10.2
I
The I
by the address byte or bytes. The control byte is preceded by a start condition. The control byte and
address byte(s) are each acknowledged by the EEPROM slave. If the EEPROM slave fails to send an
acknowledge, then the sequence is aborted and the EPC_TIMEOUT bit of the
Register (E2P_CMD)
The control byte consists of a 4-bit control code, 3-bits of chip/block select and one direction bit. The
control code is 1010b. For single byte addressing EEPROMs, the chip/block select bits are used for
address bits 10, 9, and 8. For double byte addressing EEPROMs, the chip/block select bits are set
low. The direction bit is set low to indicate the address is being written.
Figure 10.3
2
A
9
Start Condition
C EEPROM Device Addressing
A
8
2
0
R/~W
C EEPROM is addressed for a read or write operation by first sending a control byte followed
S
A
C
K
A
7
illustrates typical I
displays the various bus states of a typical I
A
6
Address Byte
A
5
change
data
can
A
4
A
3
is set.
A
2
Data Valid
or Ack
Figure 10.3 I
A
stable
1
data
A
0
A
C
K
2
C EEPROM addressing bit order for single and double byte addressing.
Figure 10.2 I
change
data
can
DATASHEET
S 1 0 1 0
2
C EEPROM Addressing
Condition
Control Byte
Re-Start
141
Chip / Block
Select Bits
Sr
2
C Cycle
0 0 0
change
data
0
can
R/~W
2
A
C
K
C cycle.
Double Byte Addressing
A
1
5
Data Valid
A
or Ack
1
4
Address High
stable
data
A
1
3
Byte
A
1
2
A
1
1
change
A
1
0
data
can
A
9
A
8
A
C
K
A
7
EEPROM Command
Stop Condition
Revision 1.7 (06-29-10)
A
6
Address Low
A
5
P
Byte
A
4
A
3
A
2
A
1
A
0
C
A
K
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