82P2821BH IDT, Integrated Device Technology Inc, 82P2821BH Datasheet - Page 20

• Manufacturer Part Number: 82P2821BH
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2821BH

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Pin Description
IDT82P2821
RCLKn / RMFn
(n=0~21)
LLOS0
Name
LLOS
Output
Output
Output
I / O
AK10, AD2, AH2, AK4, AK7, AH8,
AH20, AK22, AK25, AH26, AG29,
A28, C25, A23, A20, C19, A17,
C16, B14, D13, B11, B8
Pin No.
AF17
AF18
RCLKn: Receive Clock for Channel 0 ~ 21
When the receive system interface is configured to Single Rail NRZ Format mode, Dual Rail
NRZ Format mode or Dual Rail RZ Format mode, this multiplex pin is used as RCLKn.
RCLKn outputs a 1.544 MHz (in T1/J1 mode) or 2.048 MHz (in E1 mode) clock which is
recovered from the received signal.
The data output on RDn and RMFn (in Receive Single Rail NRZ Format mode) or RDPn/
RDNn (in Receive Dual Rail NRZ Format mode, Receive Dual Rail RZ Format mode and
Receive Dual Rail Sliced) is updated on the active edge of RCLKn. The active edge is
selected by the RCK_ES bit (b4, RCF1,...).
In LLOS condition, RCLKn output high or XCLK,
RCF0
When the receiver is powered down, RCLKn will be in High-Z state or low, as selected by the
RHZ bit (b6, RCF0,...).
RMFn: Receive Multiplex Function for Channel 0 ~ 21
When the receive system interface is configured to Dual Rail Sliced mode, this multiplex pin is
used as RMFn.
(Refer to the description of RMFn of the RDNn/RMFn multiplex pin for details).
LLOS: Receive Line Loss Of Signal
LLOS synchronizes with the output of CLKE1 and can indicate the LLOS (Line LOS) status of
all 22 channels in a serial format.
When the clock output on CLKE1 is enabled, LLOS indicates the LLOS status of the 22 chan-
nels in a serial format and repeats every twenty-two cycles. Channel 0 is positioned by
LLOS0. Refer to the description of LLOS0 below for details. The last 7 redundant clock cycles
are low and should be ignored.
LLOS is updated on the rising edge of CLKE1 and is always active high.
When the clock output of CLKE1 is disabled, LLOS will be held in High-Z state.
(Refer to Section 3.5.3.1 Line LOS (LLOS) for details.)
LLOS0: Receive Line Loss Of Signal for Channel 0
LLOS0 can indicate the position of channel 0 on the LLOS pin.
When the clock output on CLKE1 is enabled, LLOS0 pulses high for one CLKE1 clock cycle to
indicate the position of channel 0 on the LLOS pin. When CLKE1 outputs 8 KHz clock, LLOS0
pulses high for one 8 KHz clock cycle (125 µs) every twenty-nine 8 KHz clock cycles; when
CLKE1 outputs 2.048 MHz clock, LLOS0 pulses high for one 2.048 MHz clock cycle (488 ns)
every twenty-nine 2.048 MHz clock cycles. LLOS0 is updated on the rising edge of CLKE1.
When the clock output on CLKE1 is disabled, LLOS0 will be held in High-Z state.
(Refer to Section 3.5.3.1 Line LOS (LLOS) for details.)
,...)
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
(refer to Section 3.5.3.1 Line LOS (LLOS) for details).
20
Description
as selected by the RCKH bit (b7,
February 6, 2009